基于交叉耦合结构的低开销高安全性PUF电路

汪鹏君; 任明泽; 陈博; 胡双

doi:10.11999/JEIT250360

基于交叉耦合结构的低开销高安全性PUF电路

doi: 10.11999/JEIT250360 cstr: 32379.14.JEIT250360

汪鹏君^1, ,,
任明泽²,
陈博¹,
胡双²

1.
温州大学电气与电子工程学院温州 325035
2.
宁波大学信息科学与工程学院宁波 315211

基金项目: 国家自然科学基金(62174121, 62234008, 62374117)，浙江省“尖兵领雁+X”科技计划项目(2025C01063)

详细信息

作者简介:
汪鹏君：男，教授，研究方向为集成电路设计、信息安全等技术及其相关理论

任明泽：男，硕士生，研究方向为高安全高可靠物理不可克隆函数设计

陈博：男，副教授，研究方向为密码芯片攻击和防御理论及其VLSI实现

胡双：女，硕士生，研究方向为基于物理不可克隆函数的安全认证协议设计及实现

通讯作者:
汪鹏君　wangpengjun@wzu.edu.cn

中图分类号: TN43
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- 文章访问数: 62
- HTML全文浏览量: 38
- PDF下载量: 4
- 被引次数: 0
出版历程
- 收稿日期: 2025-05-06
- 修回日期: 2025-08-28
- 网络出版日期: 2025-09-02

Low-Cost and High-Security PUF Circuit Based on Cross-Coupling Structure

1.
College of Electrical and Electronic Engineering, Wenzhou University, Wenzhou 325035, China
2.
Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo 315211, China

Funds: The National Natural Science Foundation of China (62174121, 62234008, 62374117), “Vanguard Geese Leading and X” Science and Technology Program of Zhejiang Province (2025C01063)

摘要

摘要: 物理不可克隆函数(PUF)作为芯片的唯一身份标识，在资源受限的物联网设备中应用前景广阔，但面临着硬件成本过高和其自身易受攻击而导致安全性不足的问题。该文基于双稳态电路的物理特性，提出一种交叉耦合结构的低开销、高安全性强PUF电路。首先，同时激活多个双稳态单元字线，指数级提升激励响应对数量；然后，利用异或树结构混淆多路PUF，提高PUF均匀性与抗攻击能力；最后，利用Virtuoso软件在TSMC 28 nm工艺下仿真验证，并分析其抗机器学习攻击能力与统计特性。实验结果表明，当机器学习训练集激励响应对数量达10⁴时，逻辑回归、支持向量机、人工神经网络等经典机器学习算法预测率均接近50%的随机猜测，且PUF电路的随机性、唯一性和可靠性等性能均表现良好，硬件开销低于传统仲裁器PUF(APUF)，适合应用在低成本的物联网设备认证场景。
- 交叉耦合结构 /
- 机器学习 /
- 高安全性 /
- 强PUF
Abstract: Objective Physical Unclonable Functions (PUFs) serve as unique chip identifiers and have broad application in resource-constrained Internet of Things (IoT) devices. Strong PUFs are widely adopted for device authentication and state verification due to their capacity to generate exponential Challenge–Response Pairs (CRPs). However, the deterministic relationship between input and output arising from their physical construction renders them vulnerable to machine learning attacks. Attackers can model this relationship by collecting a subset of CRPs and applying algorithms such as Logistic Regression (LR), Support Vector Machines (SVM), or Artificial Neural Networks (ANN), enabling prediction of unseen CRPs. The arbiter PUF is the most representative strong PUF. To enhance its security, researchers typically employ XOR architectures or algorithmic obfuscation to increase response complexity. However, these approaches incur substantial hardware overhead, particularly when implemented in circuit form. In this study, we propose a high-security, low-cost PUF based on a cross-coupling structure that enhances resistance to machine learning attacks. The design leverages competition between bistable elements to transition from a reset to a stable state, producing exponential CRPs. Each PUF unit comprises two NOR gates and two access transistors. An XOR tree further obfuscates the output, increasing nonlinearity. Although the XOR tree requires multiple parallel outputs, the design remains compatible with embedded memory architectures such as SRAM, enabling macro-level integration. Overall, this architecture achieves improved attack resistance with minimal additional hardware, as the primary cost lies in a limited number of XOR gates. Methods A strong PUF based on a cross-coupled structure is proposed by analyzing the transient behavior of cross-coupled NOR and NAND gates transitioning from a reset state to a stable state. In this design, the word line serves as the excitation signal, and exponential CRPs are generated by sequentially traversing the word line with a fixed bit width. The implementation focuses on cross-coupled NOR gates as a representative case. Before the PUF response is generated, a reset signal drives the storage nodes of the cross-coupled NOR gates to a low level. Different digital word lines are then activated to provide excitation, while the bit lines are pre-discharged to ground. Upon deactivation of the reset signal, due to inherent process variation—specifically, mismatch in device characteristics—each activated NOR gate exhibits a unique transient response. The mismatch in strengths between different units causes competing voltage transitions at the storage nodes, resulting in a final logic state of 0 or 1 on the corresponding bit line. To reveal the intrinsic entropy mechanisms, the system is modeled by decomposing the entropy sources using the superposition principle. Two independent contributors are identified: (1) variation in charging speed induced by PMOS parasitic capacitance mismatch and (2) difference in positive feedback triggering priority due to NMOS threshold voltage mismatch. The final PUF response arises from the combined effect of these two factors. To enhance resistance to machine learning attacks, multi-bit parallel outputs from the PUF array are processed through an XOR tree. This obfuscation increases response nonlinearity, thereby improving both uniqueness and randomness while rendering the PUF immune to modeling attacks such as those based on LR, SVM, or neural networks. Results and Discussions Simulation results confirm that the proposed cross-coupled strong PUF effectively resists machine learning-based modeling attacks while maintaining favorable statistical properties in reliability, uniqueness, and randomness. The architecture demonstrates strong resilience against modeling attacks from widely used algorithms, including LR, SVM, convolutional neural networks, and ANN (Fig. 7). The average inter-slice Hamming distance is 0.4991 (standard deviation: 0.022), indicating excellent uniqueness (Fig. 8). The average intra-slice Hamming distance is 0.0926 (mean: 0.0116), confirming strong reproducibility. Output logic levels are evenly distributed, with logic 0 and logic 1 accounting for 49.97% and 50.03% of responses, respectively. The minimum Shannon entropy exceeds 0.99, and overall randomness reaches 97.64% (Figs. 9 and 10), indicating near-ideal entropy characteristics. Autocorrelation analysis shows a limit within ±0.02, aligning with the 95% confidence interval of Gaussian white noise and suggesting negligible correlation among response bits (Fig. 11). The native error rate increases from 0.9% before XOR obfuscation to 5.9% after obfuscation, reflecting the trade-off between enhanced security and response stability. Under voltage and temperature variations, the worst-case error rates after XOR obfuscation are 13.55% and 12.21%, respectively (Fig. 12), indicating robust reliability across environmental conditions. A comparative evaluation with existing strong PUF architectures is summarized in Table 1, highlighting the advantages of the proposed design in both security performance and hardware efficiency. Conclusions This study investigates the transition dynamics of bistable circuits from metastable to steady states and integrates delay-based and threshold voltage–based entropy sources to enhance the complexity of strong PUF models. The implementation of XOR tree obfuscation further increases output nonlinearity, reduces hardware overhead, and strengthens resistance to machine learning attacks. Experimental results demonstrate that, even when trained on 10⁴ CRPs, machine learning algorithms such as LR, SVM, and ANN fail to predict PUF responses. The proposed design also exhibits favorable statistical properties and strong reliability. Its structural compatibility with memory architectures makes it particularly suitable for secure authentication in memory-based IoT devices.
- Cross-coupled structures /
- Machine learning /
- High security /
- Strong Physical Unclonable Function (PUF)

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图 1 APUF结构

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图 2 亚阈值分压器PUF结构

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图 3 RSRAM-PUF单元电路结构

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图 4 CCS-PUF阵列电路

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图 5 CCS-PUF响应产生过程

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图 6 CCS-PUF整体结构

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图 7 对CCS-PUF ML攻击的测试结果

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图 8 CCS-PUF片内汉明距离和片间汉明距离

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图 9 不同CCS-PUF响应逻辑值分布与信息熵

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图 10 CCS-PUF响应二维灰度分布

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图 11 CCS-PUF自相关性

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图 12 CCS-PUF可靠性

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表 1 相关工作对比

	文献[14]	文献[11]	文献[15]	本工作
工艺(nm)	28	65	65	28
PUF类型	放大器链	亚阈值分压器	放大器链	双稳态电路
存储功能	无	无	无	有
CRPs空间	3.7×10¹⁹	1.15×10¹⁸	-	2³²
ML预测正确率(%)	49.96	51.00	50.60	52.34
温度范围(°C)	–40～100	0～50	–40～120	–20～80
电压范围(V) 可靠性(%)	0.5～1.4 89.60	0.8～1.0 89.10	0.9～1.5 91.20	0.8～1.0 86.45
唯一性(%)	50.86	50.26	50.01	49.91
随机性(%)	99.30	NIST通过	NIST通过	97.64

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参考文献(15)

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