MOS管选通的硅通孔键合前测试

窦贤锐; 梁华国; 黄正峰; 鲁迎春; 陈田; 刘军

doi:10.11999/JEIT250285

MOS管选通的硅通孔键合前测试

doi: 10.11999/JEIT250285 cstr: 32379.14.JEIT250285

1.
合肥工业大学微电子学院合肥 230601
2.
合肥工业大学计算机与信息学院(人工智能学院) 合肥 230601

基金项目: 国家自然科学基金(62027815, 62174048, 62274052)，安徽省研究生教育教学改革研究重点项目(2022jyjxggyj053)，教育部产学研合作协同育人项目(220802455302758)

详细信息

作者简介:
窦贤锐：男，博士生，研究方向为数字集成电路的可靠性设计、可测性设计，机器学习

梁华国：男，教授，研究方向为容错计算与硬件安全、嵌入式系统综合与测试、智能控制系统

黄正峰：男，教授，研究方向为数字集成电路的硬件容错设计，数字集成电路的抗辐射加固设计，数字集成电路的可靠性、可测性设计

鲁迎春：男，副教授，研究方向为集成电路硬件安全技术、集成电路抗辐照加固技术、集成电路测试技术

陈田：女，副教授，研究方向为人工智能；3D芯片与Chiplet、集成电路可测性设计；基于脑电波与生理信号的人机交互系统、情感计算

刘军：男，副教授，研究方向为嵌入式系统、基于机器学习的故障测试和机器学习加速等软件、硬件结合方面

通讯作者:
窦贤锐　dxr@hfut.edu.cn

中图分类号: TN407
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- 被引次数: 0
出版历程
- 收稿日期: 2025-04-17
- 修回日期: 2025-07-28
- 网络出版日期: 2025-08-04

MOS-gated Prebond Through-Silicon Via Testing

1.
School of Microelectronics, Hefei University of Technology, Hefei 230601, China
2.
School of Computer Science and Information Engineering (School of artificial Intelligence), Hefei University of Technology, Hefei 230601, China

Funds: The National Natural Science Foundation of China (62027815, 62174048, 62274052), The Key Project of Teaching Reform Research for Postgraduate Education in Anhui Province (2022jyjxggyj053), The Ministry of Education, Industry-University-Research Co-Operation Collaborative Education Project (220802455302758)

摘要

摘要: 在集成芯片的制造过程中，硅通孔(TSV)中可能会出现许多缺陷，这些缺陷会影响通过硅通孔信号的完整性，因此在早期生产阶段检测这些缺陷至关重要。现有的测试方法存在测试面积和时间开销大、测试精度低的问题。该文选择N型金属氧化物半导体场效应管(NMOS)和P型金属氧化物半导体场效应管(PMOS)作为选通门，以减小共享测试的面积开销；采用两级电压比较器放大测试TSV和参考电容的电压差，可以检测大于等于50 Ω的电阻性开路缺陷和小于等于9 MΩ的泄漏缺陷。与其他方案对比，该方案具有电阻性开路缺陷检测精度高、最小的测试面积和时间开销的优点。
- 集成芯片 /
- 硅通孔 /
- 键合前测试 /
- 比较器
Abstract: Objective As the miniaturization of semiconductor chips approaches physical limitations, integrated chip technologies have become essential to meet the demand for high-performance, low-cost devices in the post-Moore era. Through-Silicon Via (TSV) is a key process in advanced packaging that requires precise testing to ensure reliable interconnections. Quantitative test methods can estimate defect sizes based on test responses; however, variations in Process, Voltage, and Temperature (PVT) hinder accurate defect characterization, making the associated overhead of data capture and analysis difficult to justify. Current techniques often require long test time, with some necessitating two test cycles. While leakage defect detection has reached high accuracy, the detection of resistive open defects—sometimes only tens of milliohms in fault-free states—remains inadequate. This study presents a method that improves detection accuracy for resistive open defects and reduces both test area and time overhead, offering a more efficient and practical TSV testing solution. Methods Previous studies indicate that rising-edge testing provides higher resolution than falling-edge testing and enables simultaneous differentiation of multiple defect types. Based on this principle, a symmetric testing scheme through a single rising-edge test is proposed. To reduce the area overhead associated with shared test structures, MOS gates are employed as selection switches. NMOS transistors, due to their strong 0 and weak 1 characteristics, are placed at the driving end to enable rapid discharge and reset of the reference capacitor voltage. PMOS transistors, exhibiting strong 1 and weak 0 characteristics, are positioned at the receiving end to block interference from low-voltage signals. A two-stage comparator is then employed to amplify the voltage difference between the reference capacitor and the test TSV during the charging phase, producing two intermediate voltage levels. These are subsequently converted into standard high or low logic levels by a Schmitt trigger inverter. Based on the output logic level, both the presence and type of defect can be determined from a single test. Results and Discussions The effectiveness of the proposed method is verified through HSPICE simulations using the Nangate 45 nm open cell library. The detection accuracy for different defect types is modulated by adjusting the Width-to-Length (W/L) ratio of the MOS transistors, as shown in (Table 2). For instance, reducing the W/L ratio of NMOS transistors enhances the detection sensitivity to leakage defects. Specific W/L ratios can therefore be selected to meet targeted testing requirements. (Table 3) presents the results under PVT variations. Although the accuracy shows minor fluctuations, these remain within acceptable limits. A temperature variation of approximately 27 °C results in only a 1 Ω deviation in resistive open defect detection, and a 1 MΩ range in leakage defect accuracy. Even under the worst-case PVT condition, the minimum detection threshold for resistive open defects reaches 94 Ω, which exceeds the capability of existing methods. Conclusions A prebond TSV testing scheme based on MOS gating is proposed to address the high area and time overheads and limited accuracy of conventional approaches. The scheme adopts a symmetric structure between the reference capacitor and the test TSV to mitigate capacitance variation caused by fabrication inconsistencies. A two-stage comparator amplifies the voltage difference between the defective TSV and the reference capacitor during charging, thereby enhancing detection resolution. Simulation results indicate that the method detects resistive open defects equal of above 50 Ω and leakage defects equal of below 9 MΩ. Compared with existing methods, the proposed approach significantly reduces both testing area and time. When multiple TSVs share the testing circuitry, only one NMOS and one PMOS transistor are added, further minimizing the average area overhead.
- Integrated chip /
- Through-Silicon Via (TSV) /
- Prebond test /
- Comparator

HTML全文

图 1 TSV电气模型

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图 2 比较器

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图 3 MOS管选通的TSV键合前测试方法

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表 1 实验参数

参数	值
无故障TSV	C_TSV=60 fF, R_leak=1 TΩ
电压VDD	1 V(10%)
NMOS,PMOS: W/L	4/1(180 nm/45 nm)
C_refi	60 fF
比较器分辨率	13 mV

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表 2 测试精度与MOS管宽长比的关系

MOS管宽长比	R_open(Ω)	R_leak(MΩ)
NMOS: 4/1; PMOS: 4/1	50	9
NMOS: 6/1; PMOS: 4/1	47	5
NMOS: 8/1; PMOS: 4/1	44	3
PMOS: 6/1; NMOS: 4/1	51	8.4
PMOS: 8/1; NMOS: 4/1	52	8.0

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表 3 不同PVT下的测试精度

工艺	温度(℃)	电压(V)	R_open(Ω)	R_leak(MΩ)
TT	27	1.0	50	9
SS	27	1.0	88	25
FF	27	1.0	47	3
TT	–30	1.0	53	7
TT	0	1.0	51	8
TT	60	1.0	51	10
TT	125	1.0	52	12
TT	27	0.9	94	14
TT	27	1.1	29	7

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表 4 与其他BIST方案对比

方法	R_open(Ω)	R_leak(MΩ)	面积(μm²)	时间(μs)
[9]	30k	200	73.80	15.0
[10]	–	250	76.99	20.0
[14]	–	100	81.25	2.2
[16]	266	33	132.00	1.2
本文	50	9	31.17	0.2

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参考文献(16)

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