基于混合阶数掩码的门级电路侧信道防护方法

赵毅强; 李政阳; 张启智; 叶茂; 夏显召; 李尧; 何家骥

doi:10.11999/JEIT250198

基于混合阶数掩码的门级电路侧信道防护方法

doi: 10.11999/JEIT250198 cstr: 32379.14.JEIT250198

赵毅强^{1, 2},
李政阳^{1, 2},
张启智^{1, 2},
叶茂^{1, 2},
夏显召³,
李尧^{1, 2},
何家骥^{1, 2, ,}

1.
天津大学微电子学院天津 300072
2.
天津市成像与感知微电子技术重点实验室天津 300072
3.
中汽研科技有限公司深圳 518118

基金项目: 国家重点研发计划青年科学家项目(2023YFB4402800)，天津市科技计划项目(24YDTPJC00020)

详细信息

作者简介:
赵毅强：男，教授，研究方向为集成电路设计与安全

李政阳：男，硕士生，研究方向为集成电路设计与安全

张启智：男，博士生，研究方向为集成电路设计与安全

叶茂：男，副教授，研究方向为集成电路设计与安全

夏显召：男，博士，研究方向为汽车集成电路设计与安全

李尧：男，助理研究员，研究方向为集成电路设计与安全

何家骥：男，副教授，研究方向为集成电路设计与安全

通讯作者:
何家骥　dochejj@tju.edu.cn

中图分类号: TN918; TN791
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- 文章访问数: 229
- HTML全文浏览量: 93
- PDF下载量: 42
- 被引次数: 0
出版历程
- 收稿日期: 2025-03-24
- 修回日期: 2025-07-07
- 网络出版日期: 2025-07-11

Gate-level Side-Channel Protection Method Based on Hybrid-order Masking

ZHAO Yiqiang^{1, 2},
LI Zhengyang^{1, 2},
ZHANG Qizhi^{1, 2},
YE Mao^{1, 2},
XIA Xianzhao³,
LI Yao^{1, 2},
HE Jiaji^{1, 2
, ,}

1.
School of Microelectronics, Tianjin University, Tianjin 300072, China
2.
Tianjin Key Laboratory of Imaging and Perception Microelectronics Technology, Tianjin 300072, China
3.
CATARC Technology Co., Ltd., Shenzhen 518118, China

Funds: The National Key R&D Program Young Scientists Project (2023YFB4402800), Tianjin Science and Technology Plan Project (24YDTPJC00020)

摘要

摘要: 侧信道分析(SCA)对加密算法的电路实现造成了巨大的威胁。掩码作为硬件防护的常用手段，有效地提高了设计的抗性。但是，在已有的掩码方法中，算法级掩码要求对算法结构的深入了解并且无法保证硬件层面的强化效果；实施在寄存器传输级(RTL)电路的掩码在向硬件电路转换时，由于需要经过逻辑优化，因此难以保持结构，并且难以向高阶发展。实施在门级电路的掩码虽然有其独特的优势，但这类方法要求对泄漏精准地定位并且在部署后容易造成无法控制的开销。此外，单一阶数的掩码方法共有的局限性是，在面对比自身阶数更高的分析方法时往往难以保证防护效果。因此，为解决掩码方案共有局限和实施层级问题，该文提出一种混合阶数掩码方法。该方法针对于门级网表电路设计，融合了不同阶数掩码结构，混淆了传统的单一阶数概念，随机化了敏感变量进而大大提升设计的侧信道分析抗性。同时，该方法保证了更小的硬件开销。为了快速、有效地部署该方案，开发了自动化的掩码框架，集成了电路拓扑分析、泄漏识别和掩码防护。最终，通过模拟仿真方法，评估经过掩码的加密电路门级设计。实验结果表明，该方法实现了1 600倍以上的抗性提升，仅仅造成1.2%的额外面积开销。
- 侧信道分析 /
- 掩码防护 /
- 加密算法 /
- 功耗泄漏分析
Abstract: Objective Side-Channel Analysis (SCA) presents a significant threat to the hardware implementation of cryptographic algorithms. Among various sources of side-channel leakage, power consumption is particularly vulnerable due to its ease of extraction and interpretation, making power analysis one of the most prevalent SCA techniques. To address this threat, masking has been widely adopted as a countermeasure in hardware security. Masking introduces randomness to disrupt the correlation between sensitive intermediate data and observable side-channel information, thereby enhancing resistance to SCA. However, existing masking approaches face notable limitations. Algorithm-level masking requires comprehensive knowledge of algorithmic structure and does not reliably strengthen hardware-level security. Masking applied at the Register Transfer Level (RTL) is prone to structural alterations during hardware synthesis and is constrained by the need for logic optimization, limiting scalability. Gate-level masking offers certain advantages, yet such approaches depend on precise localization of leakage and often incur unpredictable overhead after deployment. Furthermore, many masking schemes remain susceptible to higher-order SCA techniques. To overcome these limitations, there is an urgent need for gate-level masking strategies that provide robust security, maintain acceptable overhead, and support scalable deployment in practical hardware systems. Methods To address advances in SCA techniques and the limitations of existing masking schemes, this paper proposes a hybrid-order masking method. The approach is specifically designed for gate-level netlist circuits to provide fine-grained and precise protection. By considering the structural characteristics of encryption algorithm circuits, the method integrates masking structures of different orders according to circuit requirements, introduces randomness to sensitive variables, and substantially improves resistance to side-channel attacks. In parallel, the approach accounts for potential hardware overhead to maintain practical feasibility. Theoretical security is verified through statistical evaluation combined with established SCA techniques. An automated deployment framework is developed to facilitate rapid and efficient application of the masking scheme. The framework incorporates functional modules for circuit topology analysis, leakage identification, and masking deployment, supporting a complete workflow from circuit analysis to masking implementation. The security performance of the masked design is further assessed through correlation-based evaluation methods and simulation. Results and Discussions The automated masking deployment tool is applied to implement gate-level masking for Advanced Encryption Standard (AES) circuits. The security of the masked design is evaluated through first-order and higher-order power analysis in simulation. The correlation coefficient and Minimum Traces to Disclosure (MTD) parameter serve as the primary evaluation metrics, both widely used in side-channel security assessment. The MTD reflects the number of power traces required to extract the encryption key from the circuit. In first-order power analysis, the unmasked design exhibits a maximum correlation value of 0.49 for the correct key (Fig. 6(a)), and the correlation curve for the correct key is clearly separated from those of incorrect keys. By contrast, the masked design reduces the correlation to approximately 0.02 (Fig. 6(b)), with no evidence of successful key extraction. Based on the MTD parameter, the unmasked design requires 116 traces for key disclosure, whereas the masked design requires more than 200,000 traces, reflecting an improvement exceeding 1724 times (Fig. 7). Higher-order power analysis yields consistent results. The unmasked design demonstrates an MTD of 120 traces, indicating clear vulnerability, whereas the masked design maintains a maximum correlation near 0.02 (Fig. 8) and an MTD greater than 200,000 traces (Fig. 9), corresponding to a 1667-fold improvement. In terms of hardware overhead, the masked design shows a 1.2% increase in area and a 41.1% reduction in maximum operating frequency relative to the unmasked circuit. Conclusions This study addresses the limitations of existing masking schemes by proposing a hybrid-order masking method that disrupts the conventional definition of protection order. The approach safeguards sensitive data during cryptographic algorithm operations and enhances resistance to SCA in gate-level hardware designs. An automated deployment tool is developed to efficiently integrate vulnerability identification and masking protection, supporting practical application by hardware designers. The proposed methodology is validated through correlation analysis across different orders. The results demonstrate that the method improves resistance to power analysis attacks by more than 1600 times and achieves significant security enhancement with minimal hardware overhead compared to existing masking techniques. This work advances the current knowledge of masking strategies and provides an effective approach for improving hardware-level security. Future research will focus on extending the method to broader application scenarios and enhancing performance through algorithmic improvements.
- Side-Channel Analysis (SCA) /
- Masking protection /
- Encryption algorithms /
- Power leakage analysis

HTML全文

图 1 初步2阶掩码方案

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图 2 增强的2阶掩码

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图 3 混合阶数中的1阶掩码结构图

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图 4 混合掩码方案中的高阶掩码方案(以2阶为例)

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图 5 自动化掩码工具结构框图

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图 6 掩码前后门级电路设计相关性-时间图像

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图 7 掩码前后门级电路设计相关性-功耗迹线条数图像

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图 8 面对2阶分析时掩码设计的相关性-时间点图

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图 9 面对2阶分析时掩码设计的相关性-功耗迹线条数图

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表 1 本文方法与现有工作的比较

相关工作	掩码阶数	引入的随机值(比特)	安全性提升	面积开销(%)	性能衰减
Moradi 等人^[25]	-	48	100×	359	40
Nassar等人^[15]	1	128	167×	20	34%
Koyanagi等人^[21]	1	128	10×	5.9	14%
Ramezanpour等人^[26]	1	256	7.4×	347.4	9.9%
Gross等人^[22]	1	18	>33.3×	150	20
Gross等人^[22]	2	54	～27.8×	316.7	20
Wu等人^[18]	1	128	5.1×	-	4×
本文工作	混合阶数	265	>1724×/1667×	1.2	41.1%

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