集成肖特基二极管的分裂栅碳化硅(SiC)MOSFET器件

马超; 陈伟中; 张波

doi:10.11999/JEIT250180

集成肖特基二极管的分裂栅碳化硅(SiC)MOSFET器件

doi: 10.11999/JEIT250180

马超^1, ,,
陈伟中^{2, 3},
张波¹

1.
电子科技大学成都 611731
2.
重庆邮电大学重庆 400065
3.
重庆市集成电路协同创新中心重庆 400039

基金项目: 重庆市自然科学基金面上项目(CSTB2024NSCQ-MSX1069)，重庆市创新与应用重大专项(CSTB2023TIAD-STX0014)

详细信息

作者简介:
马超：男，博士生，研究方向为半导体物理器件和集成电路

陈伟中：男，教授，研究方向为半导体功率器件设计及可靠性分析

张波：男，教授，研究方向为半导体技术

通讯作者:
马超　machao@ime.ac.cn

中图分类号: TN47‌‌
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- 被引次数: 0
出版历程
- 收稿日期: 2025-03-18
- 修回日期: 2025-03-31
- 网络出版日期: 2025-04-09

A Novel Silicon Carbide (SiC) MOSFET with Diode Integration Technology

MA Chao^{1
, ,},
CHEN Weizhong^{2, 3},
ZHANG Bo¹

1.
The State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China
2.
College of Electronics Engineering, Chongqing University of Posts and Telecommunications, Chongqing 400065, China
3.
Chongqing Integrated Circuit Collaborative Innovation Center, Chongqing 400065, China

Funds: Chongqing Nature Science Foundation of China (CSTB2024NSCQ-MSX1069), Chongqing Innovation and Application of Major Projects (CSTB2023TIAD-STX0014)

摘要

摘要: 该文提出一种集成肖特基二极管结构的新型分裂栅碳化硅MOSFET器件，有效改善传统DT-MOS器件的反向恢复与开关特性。该新型结构首先采用元胞内集成肖特基二极管技术替代传统DT-MOS的右侧沟道，其次采用分裂栅极集成技术代替传统槽栅设计，将栅极分成了栅极G和源极S两个部分，中间由二氧化硅进行介质隔离。其作用包括：集成肖特基二极管抑制体二极管导通并消除双极退化效应；集成分裂栅与源极短接，减小栅漏耦合面积来降低反馈电容与栅电荷，且在接入高电位时形成电子积累层以提高电子密度。其结果显示：反向导通状态下，电流将从肖特基二极管流出，连接源极的分裂栅极将提升电子浓度从而提高电流密度；动态开关状态下，分裂栅结构通过屏蔽设计减小了栅极与漏极的耦合面积，有效降低了米勒平台电荷Q_GD并改善了开关性能。
- 肖特基二极管 /
- 碳化硅 MOSFET双极退化效应 /
- 分裂栅极
Abstract: This paper proposes a novel double-trench Silicon Carbide (SiC) MOSFET that integrates a Schottky diode structure to improve reverse recovery and switching characteristics. In the proposed design, the conventional right-side trench channel is replaced by a Schottky diode, and a split-gate structure is connected to the source. The Schottky diode suppresses body diode conduction and eliminates the bipolar degradation effect. The split gate reduces the coupling area between the gate and drain, thereby lowering the feedback capacitance and gate charge. In addition, when the split gate is connected to a high potential, it attracts electrons to form an accumulation layer near the source, which increases electron density. During reverse conduction, the current flows through the Schottky diode, while the split gate enhances electron concentration and thus current density. The split-gate structure also shields the gate from the drain, reducing the Gate–Drain Charge (QGD) and improving switching performance. Objective Conventional Double-Trench MOSFETs (DT-MOS) typically require an external anti-parallel diode to function as a freewheeling diode in converter and inverter systems. This necessitates additional module area and increases parasitic capacitance and inductance. Utilizing the body diode as a freewheeling diode could reduce cost and save space. However, this approach presents two major challenges. First, due to the wide bandgap of SiC, the turn-on voltage of the intrinsic body diode rises significantly (approaching 3 V), which increases switching loss. This paper presents a new DT-MOS, referred to as SDT-MOS, with an integrated Schottky diode, demonstrated using TCAD SENTAURUS. In the proposed structure, the conventional right-side channel is replaced with a Schottky junction, and a source-connected split gate is embedded in the gate oxide. The SDT-MOS achieves low power consumption and reduced reverse recovery current. Methods Sentaurus TCAD is used to simulate and analyze the electrical performance of the proposed structure and its conventional counterpart. The simulation includes key physical models, such as mobility saturation under high electric fields, Auger recombination, Okuto–Crowell impact ionization, bandgap narrowing, and incomplete ionization. To improve simulation accuracy and align the results with experimental data, interface traps and fixed charges at the SiC/SiO₂ interface are also considered. Results and Discussions The Miller capacitance (Crss or C_GD) extracted at V_ds of 400 V is 29 pF/cm² for the SDT-MOS, representing a 61% reduction compared to the DT-MOS, which has a C_GD of 74 pF/cm². This reduction is primarily attributed to the integrated split-gate structure, which decreases the capacitive coupling between the gate and drain electrodes (Fig. 7). The total switching loss (Eon + Eoff) of the SDT-MOS is 1.58 mJ/cm² , which is 59.3% lower than that of the DT-MOS (3.88 mJ/cm² ), due to the improved switching characteristics enabled by the split gate (Fig. 10). In addition, the peak reverse recovery current (I_RRM) and reverse recovery charge (Q_RR) of the SDT-MOS are 165 A/cm² and 1.39 μC/cm², representing reductions of 31.3% and 54%, respectively, compared to the DT-MOS (Fig. 11). Conclusions A novel double-trench SiC MOSFET (SDT-MOS) with an integrated Schottky diode has been numerically investigated. In this structure, the right-side channel of a conventional DT-MOS is replaced with a Schottky diode, and a split gate is connected to the source. This configuration results in improved switching and reverse recovery performance. With appropriate optimization of key design parameters, the SDT-MOS retains the fundamental characteristics of a standard MOSFET. Compared with the conventional DT-MOS, the proposed device suppresses body diode conduction, mitigates bipolar degradation, and achieves a 64.9% reduction in Q_GD. Switching loss is reduced by 59.3%, and Q_RR is reduced by 54%. These enhancements make the SDT-MOS a strong candidate for high-efficiency, high–power density applications.
- Schottky diode /
- Bipolar degradation effect /
- Split gate

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图 1 横截面结构示意图

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图 2 传统DT-MOS 和提出的SDT-MOS的I-V特性对比

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图 3 新型SDT-ATMOS

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图 4 传统DT-MOS 和提出的SDT-MOS的击穿特性对比，插图为两种器件的电场分布

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图 5 新型SDT-MOS集成的肖特基二极管特性分析

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图 6 N_CSL浓度对两种器件的击穿电压与比导通电阻的影响

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图 7 SDT-MOS与DT-MOS器件的电容特性对比

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图 8 SDT-MOS与DT-MOS器件的栅极电荷特性

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图 9 双脉冲测试下DT-MOS与SDT-ATMOS器件的开关特性对比

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图 10 DT-MOS与SDT-ATMOS两种器件的开关损耗对比

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图 11 DT-MOS与SDT-MOS器件的内部二极管反向恢复特性

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表 1 两种器件关键参数

参数	DT-MOS	SDT-MOS
Cell pitch	3 μm	3 μm
T_Drift	11 μm	11 μm
W_gate	0.9 μm	0.25 μm
T_gate	1 μm	1 μm
T_ox	50 nm	20 nm
N_Drift	7×10¹⁵ cm^–3	7×10¹⁵ cm^–3
N_P-base	2.5×10¹⁷ cm^–3	2.5×10¹⁷ cm^–3
N_CSL	2.5×10¹⁶ cm^–3	2.5×10¹⁶ cm^–3
W	–	0.3 μm
T_ox2	–	0.2 μm

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表 2 两种器件的关键性能对比

参数	DT-MOS	SDT-MOS
V_cut-in	2.8 V	1.5 V
R_on,sp	1.36 mΩ·cm²	1.42 mΩ·cm²
BV	1 099 V	1 101 V
Q_GD	303 nC/cm²	106.5 nC/cm²
E_on/E_off	1.96/1.92 mJ/cm²	0.67/0.91 mJ/cm²
Q_RR	3.02 μC/cm²	1.39 μC/cm²
R_on,sp×C_GD	107.4 mΩ·pF	41.2 mΩ·pF
R_on,sp×Q_GD	412.1 mΩ·nC	151.2 mΩ·nC

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