面向通用处理器芯粒架构探索和评估的系统级模拟器

张聪武; 刘澳; 张科; 常轶松; 包云岗

doi:10.11999/JEIT240299

面向通用处理器芯粒架构探索和评估的系统级模拟器

doi: 10.11999/JEIT240299

张聪武^{1, 2},
刘澳^{1, 3},
张科^{1, 2, ,},
常轶松^{1, 2},
包云岗^{1, 2}

1.
中国科学院计算技术研究所处理器芯片全国重点实验室北京 100190
2.
中国科学院大学计算机科学科学与技术学院北京 100049
3.
郑州大学河南先进技术研究院郑州 450003

基金项目: 中国科学院战略性先导科技专项(XDA0320000, XDA0320300)，国家自然科学基金重大项目(62090020)

详细信息

作者简介:
张聪武：男，博士生，研究方向为体系结构模拟器和异构计算

刘澳：男，硕士生，研究方向为体系结构模拟器和PCIe

张科：男，博士，正高级工程师，研究方向为计算机体系结构、异构加速、FPGA云

常轶松：男，博士，高级工程师，研究方向为计算机体系结构和异构计算

包云岗：男，博士，研究员，研究方向为数据中心体系结构、处理器芯片敏捷设计方法论、开源处理器芯片生态

通讯作者:
张科　zhangke@ict.ac.cn

中图分类号: TN4; TN319
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- 被引次数: 0
出版历程
- 收稿日期: 2024-04-19
- 修回日期: 2024-11-11
- 网络出版日期: 2024-11-19

A System-level Exploration and Evaluation Simulator for chiplet-based CPU

ZHANG Congwu^{1, 2},
LIU Ao^{1, 3},
ZHANG Ke^{1, 2
, ,},
CHANG Yisong^{1, 2},
BAO Yungang^{1, 2}

1.
State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
2.
School of Computer Science and Technology, University of Chinese Academy of Sciences, Beijing 100049, China
3.
Henan Institute of Advanced Technology, Zhengzhou University, Zhengzhou 450003, China

Funds: The Strategic Priority Research Program of Chinese Academy of Sciences (XDA0320000, XDA0320300), The MajorProgram of the National Natural Science Foundation of China (62090020)

摘要

摘要: 随着摩尔定律的逐步失效，芯片制造工艺的提升愈发困难，芯片性能的提升面临“面积墙”问题，chiplet(芯粒)技术开始被广泛采用来解决此问题。然而，面向chiplet引入的架构设计参数，目前的体系结构模拟器面临新的挑战。为了能够探索chiplet架构的特定设计参数，现有工作通常只会为模拟器增加单一的功能，导致其难以用于探索多个参数对chiplet芯片的整体影响。为了能够较为全面地探索和评估chiplet芯片架构，该文基于现有gem5模拟器实现了面向通用处理器芯粒架构探索和评估的系统级模拟器(SEEChiplet)模拟器框架。首先，总结了现在chiplet芯片设计关注的3类设计参数，包括：(1) 芯片cache系统设计；(2) 封装方式模拟；(3) chiplet间的互连网络。其次，针对上述3类参数：(1)设计并实现了私有末级缓存系统，扩大了cache系统设计空间；(2) 修改了gem5已有的全局目录，以适配私有末级缓存(LLC)系统；(3) 建模了两种常见的chiplet封装方式以及chiplet间互连网络。最后，该文在SEEChiplet框架中进行了系统级的模拟评估，在被测chiplet架构通用处理器上运行操作系统及PARSEC 3.0基准测试程序，验证了SEEChiplet的功能，证明SEEChiplet可以对chiplet设计空间进行探索和评估。
- 芯粒 /
- 设计空间探索 /
- 体系结构模拟器 /
- 缓存系统
Abstract: As Moore’s Law comes to an end, it is more and more difficult to improve the chip manufacturing process, and chiplet technology has been widely adopted to improve the chip performance. However, new design parameters introduced into the chiplet architecture pose significant challenges to the computer architecture simulator. To fully support exploration and evaluation of chiplet architecture, System-level Exploration and Evaluation simulator for Chiplet (SEEChiplet), a framework based on gem5 simulator, is developed in this paper. Firstly, three design parameters concerned about chiplet chip design are summarized in this paper, including: (1) chiplet cache system design; (2) Packaging simulation; (3) Interconnection networks between chiplet. Secondly, in view of the above three design parameters, in this paper: (1) a new private last level cache system is designed and implemented to expand the cache system design space; (2) existing gem5 global directory is modified to adapt to new private Last Level Cache (LLC) system; (3) two common packaging methods of chiplet and inter-chiplet network are modeled. Finally, a chiplet-based processor is simulated with PARSEC 3.0 benchmark program running on it, which proves that SEEChiplet can explore and evaluate the design space of chiplet.
- Chiplet /
- Design space exploration /
- Computer architecture simulator /
- Cache system

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图 1 传统芯片结构和众核chiplet结构对比

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图 2 两种众核chiplet cache系统(以内存容量8GB为例)

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图 3 chiplet集成方式

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图 4 gem5片上网络连接模型

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图 5 SEEChiplet整体框架

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图 6 chiplet私有末级缓存系统建模以及读写请求处理流程

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图 7 全局目录建模及读写请求处理流程示意

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图 8 不同封装方式的实现方案

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图 9 IO-Die和Mesh拓扑

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图 10 模拟环境下不同拓扑参数下基准测试程序运行时间

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图 11 16chiplet不同核数不同拓扑，blackscholes程序运行的平均包延迟

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图 12 16chiplet不同核数配置下，blackscholes基准测试程序在模拟环境运行时的平均包跳数

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表 1 众核chiplet架构设计空间

设计选项	参数数量
chiplet本身	处理器：指令集架构；顺序执行，乱序执行；核心数量 cache系统：cache 块大小；cache容量；cache层级；chiplet私有末级缓存，全局共享末级缓存等 chiplet数量
chiplet互连架构	chiplet拓扑：Mesh, IO-die等；路由算法 chiplet互连：连接带宽；连接延迟；Router延迟 chiplet集成方式：MCM, 2.5D, 3D；chiplet与封装基板或中介层(Interposer)间SERDES配置等

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表 2 现有chiplet研究工作

研究工作	基于的模拟器或模拟手段	研究内容	chiplet封装方式	是否支持模拟运行操作系统	是否开源
Meduza^[16]	PriME^[24]	chiplet cache系统	2.5D	否	否
文献[17]	gem5^[25]	chiplet cache系统	2.5D	否	否
文献[18]	Multi2Sim^[26]	chiplet cache系统	无线连接	否	否
文献[19]	gem5-X^[27]	chiplet cache 系统	无线连接	是	否
1-Update^[20]	SimFlex^[28]	chiplet cache系统	3D	否	是
SILO^[21]	未提到	chiplet cache系统	3D	否	否
Kite^[22]	gem5	chiplet 拓扑	2D, 2.5D	是	否
HexaMesh^[23]	BookSim^[29]	chiplet 拓扑	2.5D	否	否
文献[30]	Swarm^[31]	chiplet 架构性能	2D, 2.5D	否	否
文献[32]	gem5^[24]	chiplet 架构模拟	无	是	是
DCRA^[33]	muchiSim^[34]	chiplet 架构模拟	2D, 2.5D	否	是
文献[35]	FPGA	chiplet 架构模拟	2D	是	否
SMAPPIC^[36]	FPGA	chiplet 架构模拟	无	是	是

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表 3 chiplet模拟器相关工作比较

chiplet模拟工作	全系统模拟	chiplet集成	cache系统	chiplet间网络
文献[32]	×	×	×	√
muchiSim^[34]	×	×	×	√
文献[35]	×	√	×	×
SMAPPI^C[36]	√	×	√	×
SIAM^[37]	×	×	×	√
SEEChiplet	√	√	√	√

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表 4 SEEChiplet模拟参数配置表

配置项	基本信息
CPU	Timing CPU, X86指令集，3 GHz
cache层级及相应参数(其中容量等参数可以根据用户需求配置)	3级cache, Inclusive，频率同CPU L1: 指令cache，数据cache；每个CPU核心一组；均为32 kB, 4路组相连 L2: 每个CPU一组；1MB, 8路组相连 L3：所有chiplet共享/chiplet内部共享；32 MB, 16路组相连
封装方式	MCM, 2.5D：SERDES组件增加2个cycle, Router本身3个cycle
chiplet拓扑	支持IO Die, Mesh架构
chiplet参数	每个chiplet可以有2, 4, 8, 16个核心
内存	单通道DDR4, 8 GB, 2400 MT/s

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表 5 不同末级缓存架构，chiplet内外部请求分布

末级缓存组织形式	内部请求比例(%)	外部请求比例(%)	请求总数量
chiplet私有末级缓存	78.4	21.6	458037
全局共享末级缓存	5.8	94.2	404340

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表 6 SEEChiplet建模开销总结

开销来源	开销总结
chiplet私有末级缓存	代码量：～1000行新增中间状态：12个新增事件类型：11个新增状态转移逻辑：30个，和全局目录及其他LLC进行交互新增虚通道：2个，用于和全局目录进行交互
全局目录	代码量：～600行每行新增bit数：64bit用于存放共享chiplet列表， 8 bit用于存放持有者chiplet ID 新增状态：1个基础状态S, 9个中间状态修改状态：M状态以及相关处理逻辑新增事件类型：10个
全局目录	新增状态转移逻辑：18个，全局目录转发请求，响应请求等新增虚通道：2个，用于和末级缓存进行交互

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