应用于航空航天领域的低功耗多节点抗辐射静态随机存取存储器设计

柏娜; 李钢; 许耀华; 王翊

doi:10.11999/JEIT240294

应用于航空航天领域的低功耗多节点抗辐射静态随机存取存储器设计

doi: 10.11999/JEIT240294

安徽大学集成电路学院合肥 230601

基金项目: 安徽高校协同创新项目(GXXT-2022-080, GXXT-2023-015)

详细信息

作者简介:
柏娜：女，副教授，研究方向为抗辐照集成电路设计

李钢：男，硕士生，研究方向为抗辐照集成电路设计

许耀华：男，副教授，研究方向为抗辐照通信集成电路

王翊：男，讲师，研究方向为抗辐照通信集成电路

通讯作者:
王翊　yiwang@ahu.edu.cn

中图分类号: TN402
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- 被引次数: 0
出版历程
- 收稿日期: 2024-04-17
- 修回日期: 2025-02-16
- 网络出版日期: 2025-02-25

Low-Power Multi-Node Radiation-Hardened SRAM Design for Aerospace Applications

School of Integrated Circuits, Anhui University, Hefei 230601, China

Funds: The University Synergy Innovation Program of Anhui Province (GXXT-2022-080, GXXT-2023-015)

摘要

摘要: 随着对太空的探索的深入，人们发现应用于航天领域的静态随机存取存储器(SRAM)易受到高能粒子轰击发生电节点翻转(SEU)和多节点翻转(SEMNU)。该文为解决SRAM的单粒子翻转问题提出一种16TSRAM单元可以用于SRAM的抗翻转应用，该单元包含3个敏感节点，使用金属氧化物半导体(MOS)管堆叠结构，较大提高了单元的稳定性。在65 nm CMOS工艺下仿真证明该单元可以解决SEU和SEMNU问题。相比于SARP12T, LWS14T, SAR14T, RSP14T, EDP12T, SIS10T, MNRS16T的保持静态噪声容限(HSNM)分别提升了1.4%, 54.9%, 58.9%, 0.7%, 59.1%, 107.4%。相比于SARP12T, RH10T, SAR14T, RSP14T, S8N8P16T, EDP12T, SIS10T, MNRS16T的读取静态噪声容限(RSNM)分别提升了94.3%, 31.4%, 90.3%, 8.9%, 71.5%, 90.4%, 90.3%。相较于SAR14T, RSP14T, EDP12T, RH12T, MNRS16T的保持功率(Hpwr)降低了12.4%, 16.9%, 13.1%, 50.1%。
- 单粒子翻转 /
- 抗辐射 /
- 静态随机存取存储器
Abstract: Objective As space exploration advances, the requirement for high-density memory in spacecraft escalates. However, SRAMs employed in aerospace applications face susceptibility to Single-Event Upsets (SEUs) and Multiple-Node Upsets (MNUs) due to high-energy particle bombardment, compromising the reliability of spacecraft systems. Hence, it is essential to engineer an SRAM design characterized by superior radiation resistance, reduced power consumption, and enhanced stability, fulfilling the rigorous demands of aerospace applications. Methods This paper proposes a 16T SRAM cell, designated as MNRS16T, featuring three sensitive nodes and utilizing a MOS transistor stacking structure. In this configuration, the upper tier of the stack employs a cross-coupling technique to enhance the pull-up drive capability while simultaneously diminishing that of the pull-down structure, thus balancing the driving abilities of both. The fundamental operations of the MNRS16T include write, read, and hold functions. For the write operation, bit lines WL and WWL are set to VDD, with specific MOS transistors managed to input data. During the read operation, word lines BL and BLB are precharged to VDD, and data is retrieved by assessing the voltage disparity across the bit lines. In the hold operation, bit lines are connected to ground, and word lines are precharged to VDD to preserve the data integrity. To assess the efficacy of MNRS16T, simulations are conducted using a 65nm CMOS process. Performance metrics, benchmarked against other SRAM cells include read access time, write access time, Hold Static Noise Margin (HSNM), Read Static Noise Margin (RSNM), Hold power (Hpwr), and soft error recovery capability. Results and Discussions MNRS16T exhibits superior performance across various metrics. In terms of read access time, MNRS16T exceeds other cells like SIS10T, SARP12T, and LWS14T, attributed to its efficient discharge path and optimal cell ratio (Fig. 4(a)). Regarding write access time, MNRS16T outperforms most counterparts. Specifically, its write access time is reduced compared to SARP12T, facilitated by the properties of the S1 node and the elimination of a lengthy feedback path (Fig. 4(b)). Concerning the hold static noise margin, MNRS16T achieves a higher HSNM than units such as SIS10T and RSP14T, a result of the balanced pull-up and pull-down driving forces provided by the transistor stacking structure and cross-coupling method (Fig. 5). In the RSNM assessment, although MNRS16T’s RSNM falls below that of LWS14T at elevated voltages, it remains superior to several others, including RH12T and RSP14T (Fig. 6). Regarding hold power, MNRS16T achieves reductions of 12.4%, 16.9%, 13.1%, and 50.1% relative to SAR14T, RSP14T, EDP12T, and RH12T respectively, demonstrating significant energy efficiency (Fig. 8). In simulations of soft error recovery capability, MNRS16T consistently returns to its original logic state post-SEU, even when sensitive nodes receive a 120 fC charge. Additionally, 1000 Monte Carlo simulations affirm its resilience against single-node and multi-node flips under Process, Voltage, and Temperature (PVT) variations (Fig. 3, Fig. 7). In terms of physical dimensions, MNRS16T’s 16 transistors necessitate a layout area of 3.3 μm×3.5 μm, which is comparatively larger. Finally, in the comprehensive performance index EQM, MNRS16T significantly outstrips other SRAM cells, indicating its overall performance (Fig. 9). Conclusions This paper presents the design of an MNRS16T SRAM cell tailored for aerospace applications, effectively addressing SEU and MNUs. The MNRS16T cell demonstrates reduced read and write delay times, decreased hold power, and enhanced HSNM and RSNM compared to other units. An extensive evaluation using the EQM performance index reveals that MNRS16T exceeds other radiation-hardened SRAM cells in overall performance. Nevertheless, the relatively large area of MNRS16T represents a drawback that warrants optimization in future studies.
- Single-Event Upset (SEU) /
- Radiation-resistant /
- SRAM

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图 1 MNRS16T单元

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图 2 基本操作

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图 3 MNRS16T各敏感节点受不同程度SEU和SEMNU仿真

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图 4 读取访问时间与写入访问时间比较

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图 5 保持静态噪声容限的比较

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图 6 读取静态噪声容限的比较

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图 7 MNRS16T的SEU和SEMNU蒙特卡洛仿真

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图 8 保持功率比较

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图 9 EQM综合比较

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表 1 SRAM面积比较

SRAM单元	相对面积
SARP12T	0.61
LWS14T	0.82
SAR14T	0.74
RSP14T	0.77
EDP12T	0.72
SIS10T	0.58
MNRS16T	1.00

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表 2 SRAM各项参数比较

SRAM单元	RAT(ps)	WAT(ps)	Hpwr(pw)	HSNM(V)	RSNM(V)
SARP12T	33	38	102	0.435 9	0.132 9
LWS14T	25	10	140	0.285 5	0.278 3
SAR14T	28	9	223	0.278 3	0.135 7
RSP14T	40	13	254	0.439 1	0.237 2
EDP12T	56	10	226	0.278 3	0.135 7
MNRS16T	23	8	168	0.442 4	0.258 3
SIS10T	55	11	163	0.213 3	0.135 6

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