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基于电压调控自旋轨道矩器件多数决定逻辑门的存内华莱士树乘法器设计

惠亚娟 李青朕 王雷敏 刘成

惠亚娟, 李青朕, 王雷敏, 刘成. 基于电压调控自旋轨道矩器件多数决定逻辑门的存内华莱士树乘法器设计[J]. 电子与信息学报, 2024, 46(6): 2673-2680. doi: 10.11999/JEIT230815
引用本文: 惠亚娟, 李青朕, 王雷敏, 刘成. 基于电压调控自旋轨道矩器件多数决定逻辑门的存内华莱士树乘法器设计[J]. 电子与信息学报, 2024, 46(6): 2673-2680. doi: 10.11999/JEIT230815
HUI Yajuan, LI Qingzhen, WANG Leimin, LIU Cheng. In-memory Wallace Tree Multipliers Based on Majority Gates with Voltage Gated Spin-Orbit Torque Magnetoresistive Random Access Memory Devices[J]. Journal of Electronics & Information Technology, 2024, 46(6): 2673-2680. doi: 10.11999/JEIT230815
Citation: HUI Yajuan, LI Qingzhen, WANG Leimin, LIU Cheng. In-memory Wallace Tree Multipliers Based on Majority Gates with Voltage Gated Spin-Orbit Torque Magnetoresistive Random Access Memory Devices[J]. Journal of Electronics & Information Technology, 2024, 46(6): 2673-2680. doi: 10.11999/JEIT230815

基于电压调控自旋轨道矩器件多数决定逻辑门的存内华莱士树乘法器设计

doi: 10.11999/JEIT230815
基金项目: 国家自然科学基金 (62104217)
详细信息
    作者简介:

    惠亚娟:女,副教授,研究方向为自旋器件及存储计算融合电路设计

    李青朕:男,硕士生,研究方向为自旋器件及存储计算融合电路设计

    王雷敏:男,教授,研究方向为忆阻电路设计及忆阻神经网络应用

    刘成:男,副研究员,研究方向为计算机体系结构,容错计算

    通讯作者:

    惠亚娟 huiyj@cug.edu.cn

  • 中图分类号: TN43

In-memory Wallace Tree Multipliers Based on Majority Gates with Voltage Gated Spin-Orbit Torque Magnetoresistive Random Access Memory Devices

Funds: The National Natural Science Foundation of China (62104217)
  • 摘要: 在使用新型非易失性存储阵列进行存内计算的研究中,存内乘法器的延迟往往随着位宽的增加呈指数增长,严重影响计算性能。该文设计一种电压调控自旋轨道矩磁随机存储器(VGSOT-MRAM)单元交叉阵列,并提出一种存内华莱士树乘法器的电路设计方法。所提串联存储单元结构通过电阻求和的方式,有效解决磁存储器单元阻值较低的问题;其次提出基于电压调控自旋轨道矩磁存储器单元交叉阵列的存内计算架构,利用在“读”操作期间实现的5输入多数决定逻辑门,进一步降低华莱士树乘法器的逻辑深度。与现有乘法器设计方法相比,所提方法延迟开销从O(n2)降低为O(log2 n),在大位宽时延迟更低。
  • 图  1  电压调控SOT 器件结构示意图

    图  2  VG-SOT MTJ在ISOTVg共同作用下的切换情况

    图  3  基于电压调控SOT器件的交叉阵列

    图  4  基于电压调控SOT器件的5输入多数决定逻辑门电路示意图

    图  5  基于电压调控SOT器件交叉阵列的存内计算系统架构

    图  6  4 × 4华莱士树乘法器运算原理

    图  7  4 × 4华莱士树乘法器运算到存储单元的映射规则

    图  8  输入为A = 1011和B = 1101时,基于电压调控SOT器件多数决定逻辑门的存内华莱士树乘法器仿真结果

    图  9  电压调控SOT-MRAM的版图布局

    图  10  不同类型的乘法器的延迟随乘数位宽增加的变化对比

    图  11  5输入与3输入多数决定逻辑门构成全加器的映射对比

    表  1  电压调控SOT磁隧道结模型参数

    参数 名称 数值
    tf 自由层厚度(nm) 1.1
    to MgO层厚度(nm) 1.4
    TMR 在无偏置电压时TMR比(%) 100%
    d, l, w AFM的厚度、长度、宽度(nm) 3, 50, 60
    D MTJ的直径(nm) 50
    ρch 电阻率(μ$ \Omega $·cm) 160
    θSHE 自旋霍尔角 0.25
    R·A 电阻与面积乘积($ \Omega $·μm2) 650
    Hex 交换偏置(Oe) –180
    β VCMA参数(fJ/V·M) 60
    下载: 导出CSV

    表  2  不同类型的乘法器计算延迟(cycles)和单元占用单元数量对比

    文献4 × 4 n × n
    机器周期占用单元机器周期占用单元
    [26]19520015n 2 – 11n – 115n 2 – 9n – 1
    [27]1587513n 2 – 14n + 620n – 5
    [10]13949n log2 n + 14n + 314n – 7
    [9]10238(log2 n) (10n + 2) + 4n + 22n 2 + n + 2
    [11]321286 log2 (n 2/4) + 4 [log2 2(n – log2 n)] + (n – 2) (log2 n – 2)+ 108n2 + 48 log2 (n/4)
    本文281125 log2 (n 2/4) + 4 log2 [2(n – log2 n)] + 107n2 + 42 log2 (n/4)
    下载: 导出CSV
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出版历程
  • 收稿日期:  2023-08-01
  • 修回日期:  2023-11-26
  • 网络出版日期:  2023-11-29
  • 刊出日期:  2024-06-30

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