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基于可配置延迟链的蝶形强物理不可克隆函数设计技术研究

王俊杰 戴紫彬 刘燕江

王俊杰, 戴紫彬, 刘燕江. 基于可配置延迟链的蝶形强物理不可克隆函数设计技术研究[J]. 电子与信息学报, 2023, 45(11): 3955-3964. doi: 10.11999/JEIT230805
引用本文: 王俊杰, 戴紫彬, 刘燕江. 基于可配置延迟链的蝶形强物理不可克隆函数设计技术研究[J]. 电子与信息学报, 2023, 45(11): 3955-3964. doi: 10.11999/JEIT230805
WANG Junjie, DAI Zibin, LIU Yanjiang. A Configurable Butterfly Strong Physical Unclonable Function Design Approach Based on the Delay Chain of FPGA[J]. Journal of Electronics & Information Technology, 2023, 45(11): 3955-3964. doi: 10.11999/JEIT230805
Citation: WANG Junjie, DAI Zibin, LIU Yanjiang. A Configurable Butterfly Strong Physical Unclonable Function Design Approach Based on the Delay Chain of FPGA[J]. Journal of Electronics & Information Technology, 2023, 45(11): 3955-3964. doi: 10.11999/JEIT230805

基于可配置延迟链的蝶形强物理不可克隆函数设计技术研究

doi: 10.11999/JEIT230805
基金项目: 国家自然科学基金(62302519)
详细信息
    作者简介:

    王俊杰:男,讲师,研究方向为物理不可克隆函数设计

    戴紫彬:男,教授,研究方向为可重构密码处理器设计

    刘燕江:男,讲师,研究方向为安全芯片设计

    通讯作者:

    刘燕江  liuyj_1013@126.com

  • 中图分类号: TN919; TP212

A Configurable Butterfly Strong Physical Unclonable Function Design Approach Based on the Delay Chain of FPGA

Funds: The National Natural Science Foundation of China (62302519)
  • 摘要: 物理不可克隆函数(PUF)作为芯片及系统的安全可信“根”,广泛应用在密钥管理、设备认证和指纹识别等重要领域,是目前解决芯片及系统安全问题最有效的方法之一。该文通过对PUF电路结构、工作特性和现场可编程门阵列(FPGA)结构的研究,提出一种基于可配置延迟链的蝶形强PUF (CBS-PUF)设计方法。首先利用FPGA中3种基本单元构建两条对称的可配置延迟链,并将延迟链首尾交错互联形成蝶形强PUF;然后基于FPGA搭建了PUF测试平台并开发了响应采集工具,实现激励-响应的自动化采集;最后,分析CBS-PUF的可靠性、均匀性和唯一性等性能,并讨论了抗模型攻击的具体方案。实验结果表明CBS-PUF的稳定性为99.34%,均匀性为51.02%,唯一性为47.2%,模型攻击效率最高为50.91%,可广泛应用在芯片及系统安全领域。
  • 图  1  Arbiter PUF的两条延迟链结构

    图  2  CBS-PUF结构

    图  3  CBS-PUF工作时序

    图  4  PUF测试平台与电路架构

    图  5  CBS-PUF 硬件Macro单元的布局和布线

    图  6  CBS-PUF 稳定性结果分布

    图  7  CBS-PUF 的均匀性结果分布

    图  8  CBS-PUF 的唯一性结果分布

    图  9  CBS-PUF的模型攻击测试结果

    表  1  常见PUF的性能结果比较(%)

    PUF类型 性能指标
    可靠性 均匀性 唯一性
    Arbiter PUF[1] 92.88 50.62 49.88
    SRAM PUF[3] 97.86 49.7 49.60
    PRO PUF[7] 98.01 44.79
    RPUF[8] 98.22 40.67
    MID PUF[9] 99.26 47.2
    Anderson PUF[14] 96.4 48.00
    CRO PUF[15] 96.12 50.72 47.31
    ME-RO PUF[7] 98.06 50.44 49.62
    CBS-PUF 99.34 51.02 47.20
    下载: 导出CSV
  • [1] 龚越, 叶靖, 胡瑜, 等. 内建自调整的仲裁器物理不可克隆函数[J]. 计算机辅助设计与图形学学报, 2017, 29(9): 1734–1739. doi: 10.3969/j.issn.1003-9775.2017.09.018

    GONG Yue, YE Jing, HU Yu, et al. Built-in self adjustable arbiter PUF[J]. Journal of Computer-Aided Design & Computer Graphics, 2017, 29(9): 1734–1739. doi: 10.3969/j.issn.1003-9775.2017.09.018
    [2] RAHMAN M T, RAHMAN F, FORTE D, et al. An aging-resistant RO-PUF for reliable key generation[J]. IEEE Transactions on Emerging Topics in Computing, 2016, 4(3): 335–348. doi: 10.1109/tetc.2015.2474741
    [3] GOLANBARI M S, KIAMEHR S, BISHNOI R, et al. Reliable memory PUF design for low-power applications[C]. 2018 19th International Symposium on Quality Electronic Design (ISQED), Santa Clara, USA, 2018: 207–213. doi: 10.1109/ISQED.2018.8357289.
    [4] KUMAR S S, GUAJARDO J, MAES R, et al. Extended abstract: The butterfly PUF protecting IP on every FPGA[C]. 2008 IEEE International Workshop on Hardware-Oriented Security and Trust, Anaheim, USA, 2008: 67–70. doi: 10.1109/HST.2008.4559053.
    [5] SANTIKELLUR P and CHAKRABORTY R S. A computationally efficient tensor regression network-based modeling attack on XOR arbiter PUF and its variants[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021, 40(6): 1197–1206. doi: 10.1109/TCAD.2020.3032624
    [6] AVVARU S V S, ZENG Ziqing, and PARHI K K. Homogeneous and heterogeneous feed-forward XOR physical unclonable functions[J]. IEEE Transactions on Information Forensics and Security, 2020, 15: 2485–2498. doi: 10.1109/TIFS.2020.2968113
    [7] CUI Yijun, LI Jiang, CHEN Yunpeng, et al. An efficient ring oscillator PUF using programmable delay units on FPGA[J]. ACM Transactions on Design Automation of Electronic Systems, To be published.
    [8] LIU Weiqiang, ZHANG Lei, ZHANG Zhengran, et al. XOR-based low-cost reconfigurable PUFs for IoT security[J]. ACM Transactions on Embedded Computing Systems, 2019, 18(3): 25. doi: 10.1145/3274666
    [9] ZHANG Zhengran, GU Chongyan, CUI Yijun, et al. Multi-incentive delay-based (MID) PUF[C]. 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019: 1–5.
    [10] CHEN Yongliang, CUI Xiaole, LIU Yun, et al. An evaluation method of the anti-modeling-attack capability of PUFs[J]. IEEE Transactions on Information Forensics and Security, 2023, 18: 1773–1788. doi: 10.1109/TIFS.2023.3254434
    [11] CHAMPAC V and GERVACIO J G. Timing Performance of Nanometer Digital Circuits Under Process Variations[M]. Cham: Springer, 2018: 41–67. doi: 10.1007/978-3-319-75465-9.
    [12] 朱建锋, 安建平, 王爱华. 北斗导航信号BCH译码器中校正子辅助的列表译码算法[J]. 电子与信息学报, 2014, 36(4): 1013–1016. doi: 10.3724/SP.J.1146.2013.00899

    ZHU Jianfeng, AN Jianping, and WANG Aihua. Syndrome-assisted list decoding for BCH codes of China Beidou navigation signal[J]. Journal of Electronics & Information Technology, 2014, 36(4): 1013–1016. doi: 10.3724/SP.J.1146.2013.00899
    [13] 汪鹏君, 连佳娜, 陈博. 基于序列密码的强PUF抗机器学习攻击方法[J]. 电子与信息学报, 2021, 43(9): 2474–2481. doi: 10.11999/JEIT210726

    WANG Pengjun, LIAN Jiana, and CHEN Bo. Sequence cipher based machine learning-attack resistance method for strong-PUF[J]. Journal of Electronics & Information Technology, 2021, 43(9): 2474–2481. doi: 10.11999/JEIT210726
    [14] ANDERSON J H. A PUF design for secure FPGA-based embedded systems[C]. 2010 15th Asia and South Pacific Design Automation Conference, Taipei, China, 2010: 1–6. doi: 10.1109/ASPDAC.2010.5419927.
    [15] MAITI A and SCHAUMONT P. Improved ring oscillator PUF: An FPGA-friendly secure primitive[J]. Journal of Cryptology, 2011, 24(2): 375–397. doi: 10.1007/s00145-010-9088-4
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出版历程
  • 收稿日期:  2023-08-01
  • 修回日期:  2023-10-17
  • 网络出版日期:  2023-10-26
  • 刊出日期:  2023-11-28

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