Linearization of Analog Domain Power Amplifier Based on Two-channel Nonlinear Feedback Architecture
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摘要: 该文提出一种在模拟域抑制功率放大器(PA)非线性失真的双通道非线性反馈架构，以改善PA线性度，减少邻道泄露。在该架构中，用于抑制非线性的电路包含非线性提取环路和反馈调整环路。非线性提取环路通过耦合器提取PA输入和输出信号，进行幅度和相位对齐后抵消线性信号，保留PA产生的非线性失真。反馈调整环路包含两条独立反馈通道，且信号通过非线性提取环路和反馈调整环路中两条通道分别反馈后的总时延具有两倍关系，使反馈环路呈现2阶Delta-Sigma结构形式，相比于单通道非线性反馈架构具有更好的失真抑制性能。并且通过所提方法配置反馈通道参数，可以实现不同目标频点下非线性失真的灵活抑制。最后设计了一个使用CMPA0060002F商用功放芯片的实验平台，对于带宽为40 MHz，载频为780 MHz的测试信号，在当前6 ns的硬件反馈时延条件下，可以使邻道功率泄露比(ACLR)单边带改善11 dB或双边带改善6 dB，且通过减小反馈时延能够取得更好的性能。Abstract: In this paper, a dual-channel nonlinear feedback architecture is proposed to suppress nonlinear distortion of Power Amplifiers (PA) in the analog domain to improve PA linearity and reduce adjacent channel leakage. In this architecture, a nonlinear extraction loop and a feedback adjustment loop are included to suppress the nonlinearity. First, in the nonlinear extraction loop, the PA input and output signals are extracted by a coupler and aligned with amplitude and phase. Then the two signals are combined to cancel the linear signal and obtain the nonlinear distortion generated by PA. Next, in the feedback adjustment loop, two independent analog channels are used to modify the amplitude and delay of the extracted nonlinear signal before injecting into the PA input port. The delays of these two channels can be finely tuned to ensure the whole feedback structure to behave like a second-order Delta-Sigma modulator, and it shows better distortion suppression performance compared with the single-channel nonlinear feedback architecture. By configuring the feedback channel parameters through the proposed method, flexible suppression of nonlinear distortion at different target frequency ranges can be achieved. An experimental platform using a commercial PA chip CMPA0060002F is designed for verification. For a test signal with a bandwidth of 40 MHz and a carrier frequency of 780 MHz, under the current hardware feedback delay of 6 ns, the Adjacent Channel Leakage Ratio (ACLR) single sideband can be improved by 11 dB or double sideband is improved by 6 dB, with a total feedback delay of 6 ns. Better performance can be expected by integrating this method into the PA designing stage with a reduced feedback delay.
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表 1 链路器件选型表
序号 器件类型 器件型号 S参数仿真群时延(ns) 1 PA CMPA0060002F 0.30 2 放大器 ZX60-H122+ 0.40 3 放大器 ZKL-2+ 0.45 4 衰减器 HMC346AMS8GE 0.05 5 耦合器 ZEDC-15-2B 0.36 6 耦合器 ZFDC-20-4+ 0.24 7 三合路器 ZFSC-3-4+ 0.54 8 180°合路器 SYPJ-2-13+ 0.10 9 功分器 ZESC-2-11+ 0.23 10 移相器 JSPHS-1000+ 0.96～1.8 
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表 2 双反馈功放非线性抑制实验结果
条件 反馈时延(ns) ACLR改善量(dB) 短时延通道 长时延通道 左 右 主信道陷波@780 MHz 6.2 13.3 6.0 6.0 左邻道陷波@740 MHz 5.4 10.4 11.2 6.5
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