利用多路选择器熵源的高移植性轻量级物理不可克隆函数研究

姚亮; 梁华国; 杨世豪; 章宏; 鲁迎春

doi:10.11999/JEIT221263

利用多路选择器熵源的高移植性轻量级物理不可克隆函数研究

doi: 10.11999/JEIT221263

合肥工业大学微电子学院合肥 230009

基金项目: 国家自然科学基金(62174048)

详细信息

作者简介:
姚亮：男，博士生，研究方向为硬件安全及集成电路设计

梁华国：男，教授，博士生导师，研究方向为集成电路测试、数字系统设计自动化及硬件安全

杨世豪：男，硕士生，研究方向为硬件安全及高速数据传输

章宏：女，博士生，研究方向为集成电路测试及电路模型构建

鲁迎春：男，副教授，硕士生导师，研究方向为硬件安全

通讯作者:
鲁迎春　luyingchun@hfut.edu.cn

中图分类号: TN402
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出版历程
- 收稿日期: 2022-09-30
- 修回日期: 2022-12-21
- 网络出版日期: 2022-12-23
- 刊出日期: 2023-01-17

Research on Highly Portable Lightweight Physical Unclonable Functions Using Multiplexer Entropy Sources

School of Microelectronics, Hefei University of Technology, Hefei 230009, China

Funds: The National Natural Science Foundation of China (62174048)

摘要

摘要: SR锁存器物理不可克隆函数 (Physical Unclonable Function, PUF) 是基于 FPGA 实现的最流行加密应用，在轻量级物联网设备中拥有广阔的市场。为了实现对称无偏SR锁存PUF，研究人员提出了不同的实现方法，这些方法增加了面积消耗。该文提出一种新型的基于MUX单元的延迟门来构成M_SR PUF单元，并将稳定状态下SR锁存器的输出提取作为PUF的响应。为了验证所提出的 M_SR PUF，该文在 Xilinx Virtex-6,Virtex-7 和 Kintex-7 3个系列的 FPGA 上进行了实现。值得一提的是，对称布局通过“硬宏”实现相对简单，保证了PUF更好的性能。实验结果表明，所提出的M_SR PUF可以在超宽范围的环境变化(温度：0°C～80°C；电压：0.8～1.2 V)下稳定工作，平均唯一性为50.125%。此外，所提出的 M_SR PUF 单元具有低开销的特点，仅消耗 4个 MUX 和 2个 DFF，并产生适合硬件安全应用的高熵响应。
- 硬件安全 /
- 物理不可克隆功能 /
- 对称布局 /
- 可移植性 /
- 低面积开销
Abstract: SR Latches Physical Unclonable Functions (PUFs) are the most popular FPGA-based cryptographic applications and have a broad market in lightweight IoT devices. To realize a symmetric unbiased SR latch PUF, different implementation methods that increase area consumption have been proposed. In this paper, a novel MUX-unit-based delay gate is proposed to form the M_SR PUF unit, and the output of the SR latch in the steady state is extracted as the response of the PUF. To verify the proposed M_SR PUF, it is implemented on three series of FPGAs from Xilinx Virtex-6, Virtex-7 and Kintex-7. It is worth mentioning that the symmetrical layout is relatively simple to implement through “hard macros”, which ensures better performance of PUF. The experimental results show that the proposed M_SR PUF can work stably under an ultra-wide range of environmental changes (temperature: 0°C ～80 °C; voltage: 0.8～1.2 V) with an average uniqueness of 50.125%. Furthermore, the proposed M_SR PUF unit is characterized by low overhead, consuming only 4 MUXs and 2 DFFs, and produces a high-entropy response suitable for hardware security applications.
- Hardware security /
- Physical Unclonable Functionality (PUF) /
- Symmetrical layout /
- Portability /
- Low overhead

HTML全文

图 1 传统RO PUF

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图 2 基于与非门的SR锁存器

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图 3 基于 MUX 单元的延迟门 M_NAND 设计

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图 4 提出的M_SR PUF单元

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图 5 对称比较策略

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图 6 提出的 M_SR PUF 评估系统

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图 7 22×128 bit PUF 输出序列的灰度图

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图 8 序列输出的空间特征

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图 9 Xilinx Virtex-6开发板下PUF输出序列的NIST测试

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图 10 22×128 bit PUF 输出序列的自相关测试

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图 11 3种系列 FPGA 实现的 PUF 芯片间汉明距离

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图 12 3种系类FPGA的片间汉明距离

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图 13 PUF输出响应的位翻转率

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表 1 相关PUF的性能比较

PUF 设计	FPGA平台	PUF 响应	唯一性(%)	可靠性(%)		资源消耗
PUF 设计	FPGA平台	PUF 响应	唯一性(%)	不同电压	不同温度	资源消耗
文献[8]	Spartan-3	128	49.200	80.000*		435×CLB
文献[16]	Artix	128	51.700	94.500*		–
文献[27]	Kintex-7	256	47.300	–	96.650	–
文献[27]	Artix-7	256	40.100	94.000	96.000	–
文献[9]	Spartan-3	128	46.000	>87.000		2×128 SLICEs
文献[17]	Virtex-6	128	48.438	98.242	98.326	256×CLB
本文 M_SR PUF	Virtex-6	128	50.423	94.879	97.118	4×128 MUXs 2×128 DFF
	Virtex-7		49.902	94.010	96.806
	Kintex-7		50.051	91.884	94.861
注1：*表示文献没有说明获得可靠性结果的情况. 注2：1个CLB包含2 SLICEs, 1个SLICE包含4个LUTs和8个DFFs.

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