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利用多路选择器熵源的高移植性轻量级物理不可克隆函数研究

姚亮 梁华国 杨世豪 章宏 鲁迎春

姚亮, 梁华国, 杨世豪, 章宏, 鲁迎春. 利用多路选择器熵源的高移植性轻量级物理不可克隆函数研究[J]. 电子与信息学报, 2023, 45(1): 68-77. doi: 10.11999/JEIT221263
引用本文: 姚亮, 梁华国, 杨世豪, 章宏, 鲁迎春. 利用多路选择器熵源的高移植性轻量级物理不可克隆函数研究[J]. 电子与信息学报, 2023, 45(1): 68-77. doi: 10.11999/JEIT221263
YAO Liang, LIANG Huaguo, YANG Shihao, ZHANG Hong, LU Yingchun. Research on Highly Portable Lightweight Physical Unclonable Functions Using Multiplexer Entropy Sources[J]. Journal of Electronics & Information Technology, 2023, 45(1): 68-77. doi: 10.11999/JEIT221263
Citation: YAO Liang, LIANG Huaguo, YANG Shihao, ZHANG Hong, LU Yingchun. Research on Highly Portable Lightweight Physical Unclonable Functions Using Multiplexer Entropy Sources[J]. Journal of Electronics & Information Technology, 2023, 45(1): 68-77. doi: 10.11999/JEIT221263

利用多路选择器熵源的高移植性轻量级物理不可克隆函数研究

doi: 10.11999/JEIT221263
基金项目: 国家自然科学基金(62174048)
详细信息
    作者简介:

    姚亮:男,博士生,研究方向为硬件安全及集成电路设计

    梁华国:男,教授,博士生导师,研究方向为集成电路测试、数字系统设计自动化及硬件安全

    杨世豪:男,硕士生,研究方向为硬件安全及高速数据传输

    章宏:女,博士生,研究方向为集成电路测试及电路模型构建

    鲁迎春:男,副教授,硕士生导师,研究方向为硬件安全

    通讯作者:

    鲁迎春 luyingchun@hfut.edu.cn

  • 中图分类号: TN402

Research on Highly Portable Lightweight Physical Unclonable Functions Using Multiplexer Entropy Sources

Funds: The National Natural Science Foundation of China (62174048)
  • 摘要: SR锁存器物理不可克隆函数 (Physical Unclonable Function, PUF) 是基于 FPGA 实现的最流行加密应用,在轻量级物联网设备中拥有广阔的市场。为了实现对称无偏SR锁存PUF,研究人员提出了不同的实现方法,这些方法增加了面积消耗。该文提出一种新型的基于MUX单元的延迟门来构成M_SR PUF单元,并将稳定状态下SR锁存器的输出提取作为PUF的响应。为了验证所提出的 M_SR PUF,该文在 Xilinx Virtex-6,Virtex-7 和 Kintex-7 3个系列的 FPGA 上进行了实现。值得一提的是,对称布局通过“硬宏”实现相对简单,保证了PUF更好的性能。实验结果表明,所提出的M_SR PUF可以在超宽范围的环境变化(温度:0°C~80°C;电压:0.8~1.2 V)下稳定工作,平均唯一性为50.125%。此外,所提出的 M_SR PUF 单元具有低开销的特点,仅消耗 4个 MUX 和 2个 DFF,并产生适合硬件安全应用的高熵响应。
  • 图  1  传统RO PUF

    图  2  基于与非门的SR锁存器

    图  3  基于 MUX 单元的延迟门 M_NAND 设计

    图  4  提出的M_SR PUF单元

    图  5  对称比较策略

    图  6  提出的 M_SR PUF 评估系统

    图  7  22×128 bit PUF 输出序列的灰度图

    图  8  序列输出的空间特征

    图  9  Xilinx Virtex-6开发板下PUF输出序列的NIST测试

    图  10  22×128 bit PUF 输出序列的自相关测试

    图  11  3种系列 FPGA 实现的 PUF 芯片间汉明距离

    图  12  3种系类FPGA的片间汉明距离

    图  13  PUF输出响应的位翻转率

    表  1  相关PUF的性能比较

    PUF 设计FPGA平台PUF 响应唯一性(%)可靠性(%)资源消耗
    不同电压不同温度
    文献[8]Spartan-312849.20080.000*435×CLB
    文献[16]Artix12851.70094.500*
    文献[27]Kintex-725647.30096.650
    Artix-725640.10094.00096.000
    文献[9]Spartan-312846.000>87.0002×128 SLICEs
    文献[17]Virtex-612848.43898.24298.326256×CLB
    本文 M_SR PUFVirtex-612850.42394.87997.1184×128 MUXs
    2×128 DFF
    Virtex-749.90294.01096.806
    Kintex-750.05191.88494.861
    注1:*表示文献没有说明获得可靠性结果的情况.
    注2:1个CLB包含2 SLICEs, 1个SLICE包含4个LUTs和8个DFFs.
    下载: 导出CSV
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出版历程
  • 收稿日期:  2022-09-30
  • 修回日期:  2022-12-21
  • 网络出版日期:  2022-12-23
  • 刊出日期:  2023-01-17

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