高级搜索

留言板

尊敬的读者、作者、审稿人, 关于本刊的投稿、审稿、编辑和出版的任何问题, 您可以本页添加留言。我们将尽快给您答复。谢谢您的支持!

姓名
邮箱
手机号码
标题
留言内容
验证码

一种面向序列密码的混合粒度并行运算单元

曲彤洲 戴紫彬 陈琳 刘燕江

曲彤洲, 戴紫彬, 陈琳, 刘燕江. 一种面向序列密码的混合粒度并行运算单元[J]. 电子与信息学报, 2023, 45(1): 78-86. doi: 10.11999/JEIT211579
引用本文: 曲彤洲, 戴紫彬, 陈琳, 刘燕江. 一种面向序列密码的混合粒度并行运算单元[J]. 电子与信息学报, 2023, 45(1): 78-86. doi: 10.11999/JEIT211579
QU Tongzhou, DAI Zibin, CHEN Lin, LIU Yanjiang. A Hybrid Granularity Parallel Arithmetical Unit for Stream Cipher[J]. Journal of Electronics & Information Technology, 2023, 45(1): 78-86. doi: 10.11999/JEIT211579
Citation: QU Tongzhou, DAI Zibin, CHEN Lin, LIU Yanjiang. A Hybrid Granularity Parallel Arithmetical Unit for Stream Cipher[J]. Journal of Electronics & Information Technology, 2023, 45(1): 78-86. doi: 10.11999/JEIT211579

一种面向序列密码的混合粒度并行运算单元

doi: 10.11999/JEIT211579
基金项目: 核高基国家科技重大专项(2014ZX01027-201-001)
详细信息
    作者简介:

    曲彤洲:男,博士生,研究方向为粗粒度可重构密码阵列设计

    戴紫彬:男,教授,博士生导师,研究方向为可重构计算与安全专用芯片设计

    陈琳:女,副教授,硕士生导师,研究方向为安全专用芯片设计

    刘燕江:男,博士,研究方向为芯片安全防护与硬件木马

    通讯作者:

    曲彤洲 qutongzhou@outlook.com

  • 中图分类号: TN492; TP309.7

A Hybrid Granularity Parallel Arithmetical Unit for Stream Cipher

Funds: The National Science and Technology Major Project of China (2014ZX01027-201-001)
  • 摘要: 针对可重构密码处理器对于不同域上的序列密码算法兼容性差、实现性能低的问题,该文分析了序列密码算法的多级并行性并提出了一种反馈移位寄存器(FSR)的预抽取更新模型。进而基于该模型设计了面向密码阵列架构的可重构反馈移位寄存器运算单元(RFAU),兼容不同有限域上序列密码算法的同时,采取并行抽取和流水处理策略开发了序列密码算法的反馈移位寄存器级并行性,从而有效提升了粗粒度可重构阵列(CGRA)平台上序列密码算法的处理性能。实验结果表明与其他可重构处理器相比,对于有限域(GF)(2)上的序列密码算法,RFAU带来的性能提升为23%~186%;对于GF(2u)域上的序列密码算法,性能提升达约66%~79%,且面积效率提升约64%~91%。
  • 图  1  序列密码算法和CGRA基本结构

    图  2  序列密码算法FSR级并行性

    图  3  FSR更新过程图示

    图  4  RFAU结构框图

    图  5  ZUC算法状态反馈函数

    图  6  采用延迟抽取技术后的流水实现DFG

    图  7  GF(2)上序列密码算法实现性能对比

    表  1  4×4规模的RFAU硬件性能参数

    符号定义
    FP序列密码算法函数级并行性
    RP序列密码算法FSR级并行性
    OP序列密码算法操作级并行性
    lFSR中的寄存器位宽
    nFSR中的寄存器数量
    rxtFSR中寄存器Regx在时刻tt+i的状态
    an寄存器n的状态值
    axmRegx中第m bit
    StFSR中在时刻t的状态
    FFSR的状态反馈函数
    $ {r_{{F_z}}} $FSR中参与反馈函数的寄存器状态:状态变量
    kFSR中参与反馈函数的状态变量数量
    Rt时刻t所有状态变量构成的集合Rt
    d反馈端和距它最近的状态变量之间的距离d
    下载: 导出CSV

    表  2  GF(232)上序列密码算法实现性能及面积效率对比

    结构工艺
    (nm)
    面积
    (mm2)
    算法工作频率
    (MHz)
    吞吐率
    (Gbps)
    面积效率算法工作频率
    (MHz)
    吞吐率
    (Gbps)
    面积效率
    本文5512.35Snow 3G2507.810.63ZUC2226.940.56
    PVHarray5512.251304.370.351253.910.32
    Anole657.754006.40.834003.20.41
    文献[12]402.543503.871.523504.681.84
    本文
    PVHarray
    55
    55
    12.35
    12.25
    Sober-t32240
    130
    7.5
    4.37
    0.61
    0.35
    SOSEMANUK200
    120
    6.25
    3.75
    0.51
    0.31
    下载: 导出CSV
  • [1] KOTESHWARA S, KUMAR M, and PATTNAIK P. Performance optimization of lattice post-quantum cryptographic algorithms on many-core processors[C]. 2020 IEEE International Symposium on Performance Analysis of Systems and Software, Boston, USA, 2020: 223–225.
    [2] JIAO Lin, HAO Yonglin, and FENG Dengguo. Stream cipher designs: A review[J]. Science China Information Sciences, 2020, 63(3): 131101. doi: 10.1007/s11432-018-9929-x
    [3] DAI Zibin, LI Wei, CHEN Tao, et al. Design and implementation of a high-speed reconfigurable feedback shift register[C]. 2008 4th IEEE International Conference on Circuits and Systems for Communications, Shanghai, China, 2008: 338–342.
    [4] 徐光明, 徐金甫, 常忠祥, 等. 序列密码非线性反馈移存器的可重构研究[J]. 计算机应用研究, 2015, 32(9): 2823–2826. doi: 10.3969/j.issn.1001-3695.2015.09.062

    XU Guangming, XU Jinfu, CHANG Zhongxiang, et al. Reconfigurability study on nonlinear feedback shift registers in stream cipher[J]. Application Research of Computers, 2015, 32(9): 2823–2826. doi: 10.3969/j.issn.1001-3695.2015.09.062
    [5] NAN Longmei, ZENG Xiaoyang, WANG Zhouchuang, et al. Research of a reconfigurable coarse-grained cryptographic processing unit based on different operation similar structure[C]. The 2017 IEEE 12th International Conference on ASIC, Guiyang, China, 2017: 191–194.
    [6] NAN Longmei, YANG Xuan, ZENG Xiaoyang, et al. A VLIW architecture stream cryptographic processor for information security[J]. China Communications, 2019, 16(6): 185–199. doi: 10.23919/JCC.2019.06.015
    [7] 管子铭. 序列密码可重构处理结构研究与设计[D]. [硕士论文], 解放军信息工程大学, 2009.

    GUAN Ziming. Research and design of sequence cipher reconfigurable processing architecture[D]. [Master dissertation], PLA Information Engineering University, 2009.
    [8] DU Yiran, LI Wei, DAI Zibin, et al. PVHArray: An energy-efficient reconfigurable cryptographic logic array with intelligent mapping[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020, 28(5): 1302–1315. doi: 10.1109/TVLSI.2020.2972392
    [9] LIU Leibo, WANG Bo, DENG Chenchen, et al. Anole: A highly efficient dynamically reconfigurable crypto-processor for symmetric-key algorithms[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, 37(12): 3081–3094. doi: 10.1109/TCAD.2018.2801229
    [10] SAYILAR G and CHIOU D. Cryptoraptor: High throughput reconfigurable cryptographic processor[C]. 2014 IEEE/ACM International Conference on Computer-Aided Design, San Jose; USA, 2014: 155–161.
    [11] IBRAHIM M I, KHAN M I W, JUVEKAR C S, et al. 29.8 THzID: A 1.6mm2 package-less cryptographic identification tag with backscattering and beam-steering at 260GHz[C]. 2020 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, USA, 2020: 454–456.
    [12] 杨锦江. 基于可重构计算的密码处理器关键技术研究[D]. [博士论文], 东南大学, 2018.

    YANG Jinjiang. Research on key technologies of reconfigurable cryptographic processors[D]. [Ph. D. dissertation], Southeast University, 2018.
    [13] XUE Yuqian and DAI Zibin. Reconfiurable multi-launch pipeline processing architecture for block cipher[J]. Application of Electronic Technique, 2020, 46(4): 40–44,48. doi: 10.16157/j.issn.0258-7998.200005
    [14] KITSOS P, SKLAVOS N, PROVELENGIOS G, et al. FPGA-based performance analysis of stream ciphers ZUC, Snow3g, grain V1, mickey V2, trivium and E0[J]. Microprocessors and Microsystems, 2013, 37(2): 235–245. doi: 10.1016/j.micpro.2012.09.007
    [15] STILLMAKER A and BAAS B. Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm[J]. Integration, 2017, 58: 74–81. doi: 10.1016/j.vlsi.2017.02.002
  • 加载中
图(7) / 表(2)
计量
  • 文章访问数:  129
  • HTML全文浏览量:  40
  • PDF下载量:  9
  • 被引次数: 0
出版历程
  • 收稿日期:  2021-12-28
  • 修回日期:  2022-06-06
  • 网络出版日期:  2022-06-07
  • 刊出日期:  2023-01-17

目录

    /

    返回文章
    返回