基于FPGA的图着色问题求解

张益豪; 张子超; 刘小青; 冷煌; 王之元; 许进

doi:10.11999/JEIT210646

基于FPGA的图着色问题求解

doi: 10.11999/JEIT210646

张益豪¹,
张子超¹,
刘小青^{1, 2},
冷煌^{1, 2},
王之元^3, ,,
许进^{1, 2}

1.
北京大学信息科学技术学院北京 100871
2.
北京大学高可信软件技术教育部重点实验室北京 100871
3.
国防科技创新研究院人工智能研究中心北京 100073

基金项目: 国家重点研发计划(2019YFA0706401)，国家自然科学基金(61632002, 61872166, 61902005, 62002002)

详细信息

作者简介:
张益豪：男，博士，研究方向为信号处理、非凸优化、组合优化

张子超：男，博士生，研究方向为社交网络、图神经网络与生物信息网络等

刘小青：女，特聘副研究员，研究方向为图论与组合优化、新型计算

冷煌：男，特聘副研究员，研究方向为新型计算、生物计算、组合优化

王之元：女，副研究员，研究方向为智能模型、智能算法

许进：男，教授，研究方向为图论与组合优化、生物计算机、社交网络与信息安全等

通讯作者:
王之元　alice_zyw@foxmail.com

中图分类号: O157.6
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- 被引次数: 0
出版历程
- 收稿日期: 2021-06-25
- 修回日期: 2022-02-28
- 录用日期: 2022-01-20
- 网络出版日期: 2022-02-19
- 刊出日期: 2022-09-19

Solution of Graph Coloring Problem Based on FPGA

ZHANG Yihao¹,
ZHANG Zichao¹,
LIU Xiaoqing^{1, 2},
LENG Huang^{1, 2},
WANG Zhiyuan^{3
, ,},
XU Jin^{1, 2}

1.
School of Electronic Engineering and Computer Science, Peking University, Beijing 100871, China
2.
Key Laboratory of High Confidence Software Technologies, Peking University, Beijing 100871, China
3.
Artificial Intelligence Research Center, Defense Innovation Institute, Beijing 100073, China

Funds: The National Key Research and Development Program (2019YFA0706401), The National Natural Science Foundation of China (61632002, 61872166, 61902005, 62002002)

摘要

摘要: 图着色问题是在满足相邻顶点不能分配相同颜色且颜色数最少的约束条件下，将图的顶点划分为不相交的集合，且每个集合中的顶点分配相同的颜色。由于图着色问题属于NP-完全问题，求解图着色问题的算法复杂度会随顶点个数的增加呈指数级增长。当顶点个数非常大时，通用处理器求解图着色问题的性能将会显著下降。因此，该文基于现场可编程逻辑门阵列(FPGA)实现求解图着色算法的专用硬件加速器。首先依据FPGA模块化的设计思路提出并实现了基于回溯法的图着色问题求解的硬件架构；其次分析了FPGA内部消耗资源与图着色顶点数之间的关系；最后利用通用异步收发传输器协议实现了通用处理器与FPGA的通信。实验结果表明，相比于在通用处理器上利用软件实现图着色算法，基于FPGA所实现的图着色算法运行时间减少了一个数量级。除此之外，FPGA内部消耗资源数与顶点个数呈线性关系，且每次迭代时FPGA运算所消耗的时间与顶点个数无关。
- 图着色问题 /
- 回溯法 /
- FPGA
Abstract: Graph coloring problem divides the vertices of the graph into disjoint sets and the vertices in each set are assigned by the same color under the constraints that adjacent vertices can not be assigned the same color and the number of colors is the smallest. Since graph coloring problem belongs to the class of NP-complete problems, the complexity for solving the graph coloring problem increases exponentially with the number of vertices. The performance of solving graph coloring problem by general-purpose processors decreases significantly when the number of vertices is large enough. This paper implements a dedicated hardware accelerator for solving graph coloring problem based on Field Programmable Gate Array (FPGA). Firstly, by utilizing the rule of FPGA modular design, the hardware architecture for solving graph coloring problem based on the backtracking is proposed and implemented. Secondly, the relationship between the resource consumption of FPGA and the number of vertices is analyzed. Finally, the general-purpose processor and FPGA can communicate through universal asynchronous transmitter-receiver protocol. The experimental results show that the running time of graph coloring algorithm based on FPGA is about an order of magnitude smaller than that of graph coloring algorithm based on software on general-purpose processors. Besides, the resource consumption of FPGA is linear with the number of vertices and the time consumption at each iteration is independent of the number of vertices.
- Graph coloring problem /
- Backtracking /
- FPGA

HTML全文

图 1 四顶点平面图

下载: 全尺寸图片幻灯片

图 2 四顶点平面图的着色方案

下载: 全尺寸图片幻灯片

图 3 回溯法算法流程图

下载: 全尺寸图片幻灯片

图 4 基于FPGA的图着色实现方案

下载: 全尺寸图片幻灯片

图 5 顶点着色方案验证的功能仿真

下载: 全尺寸图片幻灯片

图 6 12顶点图的邻接矩阵

下载: 全尺寸图片幻灯片

表 1 FPGA资源消耗

图的顶点个数
12 16 32 64 128 256 512

LE 499 547 717 1045 1700 2997 5580
寄存器 262 323 439 667 1119 2019 3815

下载: 导出CSV

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