Design of Hardware IP Core Security Protection Based on Multi-Level Co-obfuscation
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摘要: 传统硬件混淆从物理级、逻辑级、行为级等进行单层次混淆，没有发挥多级协同优势，存在安全隐患。该文通过对物理版图、电路逻辑和状态跳变行为的关系研究，提出多级协同混淆的硬件IP核防护方法。该方案首先在自下而上协同混淆中，采用虚拟孔设计版图级伪装门的方式进行物理-逻辑级混淆，采用过孔型物理不可克隆函数(PUF)控制状态跳变的方式实现物理-行为级混淆；然后，在自上而下协同混淆中，利用密钥控制密钥门进行行为-逻辑级混淆，利用并行-支路混淆线的方法完成行为-物理级混淆；最后提出混淆电路在网表的替换机制，设计物理-逻辑-行为的3级协同混淆，实现多级协同混淆的IP核安全防护。ISCAS-89基准电路测试结果表明，在TSMC 65 nm工艺下，多级协同混淆IP核在较大规模测试电路中的面积开销占比平均为11.7%，功耗开销占比平均为5.1%，正确密钥和错误密钥下的寄存器翻转差异低于10%，所提混淆方案可有效抵御暴力攻击、逆向工程、SAT等攻击。Abstract: Most of the reported hardware obfuscations are single-level ones focusing on physical level, logical level or behavior level, in which the lack of synergy among different levels commonly results in limited security performance. Based on study of the relationships among circuit layout, logic and states transition, a multi-level co-obfuscation scheme is proposed to protect hardware IP cores. In bottom-up collaborative confusion design, dummy vias are introduced into camouflage gates layout to perform physical-logic obfuscation, and via-PUF (Physical Unclonable Fuction) are utilized in state transition control to realize physical-behavior obfuscation. Then, in top-down collaborative obfuscation design, logic locks are used to perform behavior-logic obfuscation, and parallel-branch obfuscation wire technique is designed to complete the behavior-physical confusion. Finally, a substitution algorithm of the obfuscation gates into the circuit’s netlist is proposed, and the three-level cooperative obfuscation is realized to achieve IP core security protection. ISCAS-89 Benchmarks and a typical cryptogram algorithm are used to verify the correctness and efficiency of the proposed IP core protection scheme. The test results show that under TSMC 65nm process, the average area cost percentage of the proposed co-obfuscation in large-scale circuits is 11.7%, the average power consumption accounts for 5.1%, The difference of register toggle between correct and wrong keys is less than 10%, and the proposed scheme can effectively resist violence attack, reverse engineering, boolean SATisfiability (SAT) attack.
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表 1 与非、或非、反相器伪装门的接触孔配置
逻辑门 接触孔 过孔 Dummy True Dummy True NAND 4 1 2 3 5 6 3 6 1 2 4 5 NOR 2 4 5 1 2 4 5 6 1 4 2 3 5 6 INV / 1 2 3 4 5 6 3 4 1 2 5 6 
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表 2 异或门和与门密钥门接触孔配置
逻辑门 接触孔 True Dummy XOR 1 2 4 5 6 7 8 11 3 9 10 12 AND 1 3 6 8 9 10 11 12 2 4 5 7
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表 3 混淆单元插入/替换算法伪代码
输入：原始网表，密钥数据，时序报告 输出：混淆网表 (1) Key Gatelocation={}; (2)将关键路径上的门单元存放到Key Gatelocation; (3) For i←2 to Key size do (4) 搜索原始网表中第i个符合条件的门 Gatei (5) 如果 Gatei不在CriticalPath_ Gate中， (6) 则把其地址存入数组Key Gatelocation; (7) end (8) 替换混淆单元门； (9) 在输出选择门中插入密钥门； (10) 插入新的输入端口和互连线； (11) 更新电路网表； (12) 结束
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表 4 所提混淆与已有方案的相关性能
文献 类型 硬件开销 安全性 基准 面积(%) 功耗(%) 时延 SAT RE BFA RA [2] Practical Logic Obfuscation s9234 0.56 4.57 0.94 GB – √ – – [10] Dynamic State-Deflection s9234 11.00 5.30 0.94 GB – – – – [11] DUP s9234 42.70 34.10 0.98 GB √ – √ – [12] ISO s9234 25.80 3.80 0.94 GB √ – – – [13] SARLock s9234 6.80 13.30 0.89 GB √ – – – [14] Camouflage gate s9234 7.20 28.10 0.73 GB – √ – – 本文 Multi-level Obfuscation s9234 29.30 3.40 0.47 GB √ √ √ √
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