基于局部逻辑伪装的IC保护方法

杨然; 高文超

doi:10.11999/JEIT210577

基于局部逻辑伪装的IC保护方法

doi: 10.11999/JEIT210577

杨然¹,
高文超^2, ,

1.
中国矿业大学数学学院徐州 221116
2.
中国矿业大学(北京)机电与信息工程学院北京 100083

基金项目: 国家自然科学基金(61834002)，北京信息科学与技术国家研究中心(BNR2019ZS01001)

详细信息

作者简介:
杨然：女，1973年生，工程师，研究方向为大规模数值计算、组合优化算法

高文超：女，1986年生，副教授，研究方向为时空大数据、计算机辅助设计

通讯作者:
高文超　gaowc@cumtb.edu.cn

中图分类号: TP331
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- 被引次数: 0
出版历程
- 收稿日期: 2021-06-15
- 修回日期: 2021-08-12
- 网络出版日期: 2021-08-23
- 刊出日期: 2021-09-16

Local Logic Camouflaging Based IC Circuit Protection Method

Ran YANG¹,
Wenchao GAO^{2
, ,}

1.
School of Mathematics, China University of Mining and Technology, Xuzhou 221116, China
2.
College of Mechanical Electronic & Information Engineering, China University of Mining & Technology (Beijing), Beijing 100083, China

Funds: The National Natural Science Foundation of China (61834002), Beijing National Research Center for Information Science and Technology (BNR2019ZS01001)

摘要

摘要: 集成电路(IC)设计面临逆向工程的攻击，核心专利(IP)和算法被盗用，硬件安全受到威胁。该文提出一种电路伪装方法LPerturb，通过对其局部电路逻辑的扰动，实现IC电路的保护。对电路进行最大独立锥划分(MFFCs)，选取被伪装的最大子电路，确保输出逻辑扰动的局部性。针对要扰动锥结点逻辑，从锥中选择被替换的逻辑单元，以最小化代价对进行局部电路逻辑扰动。用多值伪装电路对扰动的逻辑值进行混淆保护，恢复相应的电路逻辑。实验结果表明，该方法能够稳定生成保护电路，具有较好的输出扰动性，能有效抵御SAT去伪装攻击，面积额外开销较小，时延影响可以忽略。
- 硬件安全 /
- IC电路保护 /
- IC伪装 /
- 逻辑混淆 /
- 最小项扰动
Abstract: With illegal hardware reverse engineering attacks, the Integrated Circuit (IC) design suffers from the key Intellectual Property (IP)/algorithm piracy and hardware Trojan insertion. An IC camouflaging method, LPerturb, is proposed in this paper by local circuit logic perturbation for IP Protection. The circuit is partitioned into some Maximum Fanout-Free Cones (MFFCs), namely multiple functionally independent sub-circuits to be camouflaged, for output logic perturbation locally. A logic cell is selected in the MFFC sub-circuit. The cell is replaced to perturb the logic functionality of the MFFC minimally. A multi-logic camouflaged block is used to protect and restore the perturbed logic secret. Experimental results show that LPerturb can produce the camouflaged circuits steadily, which has good output corruptibility and effectively resists SAT based attack. The overhead in area and timing is also in low level.
- Hardware security /
- IC protection /
- IC camouflaging /
- Logic obfuscation /
- Minterm perturbation

HTML全文

图 1 INV/BUF伪装单元结构^[14]

下载: 全尺寸图片幻灯片

图 2 CamoPerturb结构^[14]

下载: 全尺寸图片幻灯片

图 3 最大独立锥电路划分示例

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图 4 逻辑单元G₄最小项扰动计算

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图 5 输入映射模块(产生m₁₂和m₁₃的CI编码)

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图 6 (INV, BUF, BUF, INV)硬编码密钥生成模块^[14]

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图 7 密钥确认模块^[14]

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图 8 使用SAT攻击伪装技术的时间开销

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图 9 输出数据扰动性汉明距离比较

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表 1 逻辑伪装方法LPerturb伪代码

输入：原始网表C_orig；
输出：伪装网表C_camo；
(1)利用最大独立锥划分方法，提取最大独立扰动子电路集{C_MMFCi}；
(2)for 最大独立扰动子电路C_MMFCi {
计算逻辑门的扰动最小项集合；
选择替换逻辑单元和扰动最小项集合；
确定逻辑门替换逻辑及电路；
生成子电路扰动电路Cⁱ_pert和伪装模块Cⁱ_CamoFix子电路；
生成伪装子电路Cⁱ_camo }
(3)生成伪装电路C_camo

下载: 导出CSV

表 2 逻辑单元G₄影响最小项

输入向量		影响最小项SMA(i₁,i₂)	G_orig	G_trans
e	f	影响最小项SMA(i₁,i₂)	XNOR	AND	NOR	Fun1	Fun2
0	0	{ }	1	0	1	1	1
0	1	{m₁₂(abc'd'),m₁₃(abc'd)}	0	0	0	1	0
1	0	{m₁₅(abcd)}	0	0	0	0	1
1	1	{m₁₄(abcd')}	1	1	0	1	1

下载: 导出CSV

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