FPGA三模冗余工具的关键技术与发展

陈雷; 张瑶伟; 王硕; 周婧; 田春生; 庞永江; 马筱婧; 周冲; 杜忠

doi:10.11999/JEIT210330

FPGA三模冗余工具的关键技术与发展

doi: 10.11999/JEIT210330

陈雷¹,
张瑶伟^1, ,,
王硕¹,
周婧¹,
田春生^{1, 2},
庞永江¹,
马筱婧¹,
周冲¹,
杜忠¹

1.
北京微电子技术研究所北京 100076
2.
北京大学信息科学技术学院北京 100871

基金项目: 国家科技重大专项(2009ZYHJ0005)

详细信息

作者简介:
陈雷：男，1978年生，研究员，主要研究方向为FPGA，Soc，ASIC等VLSI研发

张瑶伟：男，1997年生，硕士生，主要研究方向为FPGA的三模冗余、高层次综合

王硕：男，1985年生，硕士，主要研究方向为FPGA CAD算法

周婧：女，1986年生，硕士，主要研究方向为故障注入、刷新技术、单粒子效应缓解技术

田春生：男，1993年生，博士，主要研究方向为集成电路设计自动化

庞永江：男，1991年生，硕士，主要研究方向为软件应用、IDE设计

马筱婧：女，1993年生，硕士，主要研究方向为FPGA应用与验证

周冲：男，1995年生，硕士，主要研究方向为综合、布局、布线

杜忠：男，1975年生，研究员，主要研究方向为软件应用、抗辐照技术、FPGA测试、FPGA EDA

通讯作者:
张瑶伟　zyw18810532787@163.com

中图分类号: TN47
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- 被引次数: 0
出版历程
- 收稿日期: 2021-04-20
- 修回日期: 2022-03-23
- 网络出版日期: 2022-04-12
- 刊出日期: 2022-06-21

Key Technology and Development of Triple Modular Redundancy Tool for FPGA

1.
Beijing Microelectronics Technology Institute, Beijing 100076, China
2.
School of Electronics Engineering and Computer Science, Peking University, Beijing 100871, China

Funds: The National Science and Technology Major Project (2009ZYHJ0005)

摘要

摘要: SRAM型现场可编程门阵列(FPGA)在空间辐射环境中容易受到单粒子效应的影响，从而发生软错误，三模冗余技术(TMR)是目前使用最广泛的缓解FPGA软错误的电路加固技术。该文首先介绍了三模冗余技术研究现状，然后总结了三模冗余工具常用的细粒度TMR技术、系统分级技术、配置刷新技术、状态同步技术4项关键技术及其实现原理。随着FPGA的高层次综合技术愈发成熟，基于高层次综合的三模冗余工具逐渐成为新的研究分支，该文分类介绍了当前主流的基于寄存器传输级的三模冗余工具，基于重要软核资源的三模冗余工具，以及新兴的基于高层次综合的三模冗余工具，最后对FPGA三模冗余工具的未来发展趋势进行了总结与展望。
- 现场可编程门阵列 /
- 单粒子效应 /
- 软件 /
- 三模冗余技术 /
- 高层次综合
Abstract: SRAM-based FPGAs are sensitive to single event effect in space radiation environment, resulting in soft errors. Triple Modular Redundancy (TMR) is the most widely used circuit hardening technology to alleviate FPGA soft errors. This paper introduces first the current research status of TMR technology, and then summarizes four key technologies and their implementation principles of fine-grained TMR technology, system partitioning technology, configuration scrubbing technology and state synchronization technology, which are commonly used in TMR tools. As the high-level synthesis technology of FPGA becomes more and more mature, the TMR tools based on high level synthesis have gradually become a new research branch. The current mainstream TMR tools based on the register transfer level, TMR tools based on important soft-core resources, and the emerging TMR tools based on high-level synthesis are classified and introduced. Finally, the future development trend of TMR tool for FPGA is summarized and forecasted.
- Field Programmable Gate Array (FPGA) /
- Single event effect /
- Software /
- Triple Modular Redundancy (TMR) /
- High level synthesis

HTML全文

图 1 细粒度的TMR技术分类

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图 2 将TMR应用于分解的系统

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图 3 分级TMR系统中的容错与故障

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图 4 不带状态同步的TMR

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图 5 带状态同步的TMR

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图 6 关键技术的配合使用

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图 7 RASP-TMR生成的顶层文件结构

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图 8 TMRTool的实现

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图 9 SEU的检测与恢复状态机

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图 10 RTL设计与HLS设计的设计时间与应用性能

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图 11 新型容错硬件加速器设计

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图 12 MicroBlaze TMR子系统的部分结构图

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表 1 现有的TMR工具

分类	特点	工具	特点
基于RTL	可以实现对TMR实现细节的微调，面临综合阶段冗余被优化的问题，需要掌握综合阶段的各种中间网表文件的细节	RASP-TMR	Verilog语言的TMR，基于MATLAB开发，功能简单
		TMRG	Verilog语言的TMR，使用Python编写，维护积极，适合学术交流
		Xilinx TMRTool	RTL级.ngc网表文件的TMR，受国际武器贸易条例保护
		BL-TMR	RTL级.edif网表文件的TMR，开源版本早已停止更新
		Mentor Precision Hi-Rel	RTL综合阶段TMR，采用细粒度TMR技术，基于汉明编码的安全状态机策略
		Synopsys Synplify Premier	RTL综合阶段TMR，与Mentor的工具类似，网上可查阅的资料少
基于HLS	大幅缩短设计周期，提供流水线设计，减轻 TMR设计带来的负面时序影响，对设计进行HLS空间探索	TLegUp	HLS阶段的TMR，构建该方向的大框架，受商业化的限制，更新停滞
基于HLS	大幅缩短设计周期，提供流水线设计，减轻 TMR设计带来的负面时序影响，对设计进行HLS空间探索	C-TMR	C语言的TMR，可对设计进行HLS空间探索，还未形成完成工具
基于软核	对软核提供了功能完备的保护，但仅针对MicroBlaze提供TMR优化，使用范围单一局限	Xilinx Vivado MicroBlaze TMR	软核的TMR，5个IP组成的TMR子系统，自动管理和屏蔽影响MicroBlaze软核的故障

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参考文献(47)

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