Design of Low-jitter, Multi-phase Clock Generation Circuit for Geiger-mode Avalanche Focal Plane Array Applications
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摘要: 针对单光子探测盖革雪崩焦平面读出电路应用，基于全局共享延迟锁相环和2维H型时钟树网络，该文设计一款低抖动多相位时钟电路。延迟锁相环采用8相位压控延迟链、双边沿触发型鉴相器和启动-复位模块，引入差分电荷泵结构，减小充放电流失配，降低时钟抖动。采用H时钟树结构，减小大规模电路芯片传输路径不对称引起的相位差异，确保多路分相时钟等延迟到达像素单元。采用0.18 µm CMOS工艺流片，测试结果表明，延迟锁相环锁定频率范围150～400 MHz。锁定范围内，相位噪声低于–127 dBc/Hz@1 MHz，时钟RMS抖动低于2.5 ps，静态相位误差低于65 ps。Abstract: A low-jitter multi-phase clock generation circuit is designed based on a global shared Delay Locked Loop (DLL) and a two-dimensional H-shaped clock tree network for Geiger-mode avalanche focal plane array applications. The DLL adopts an eight-phase voltage-controlled delay chain, a double-edge trigger phase detector and a start reset module. A differential charge pump structure is introduced to reduce the current mismatch between charging and discharging and lower the clock timing jitter. H clock tree structure is involved to diminish the phase variation induced by the asymmetry of the transmission route for large scale integrated circuit, ensuring an equal delay of the multi-channel split-phase clock signal to the pixel unit. The locking frequency range of 150～400 MHz, phase noises below -127 dBc/Hz at 1 MHz offset, RMS timing jitter of below 2.5 ps and static phase error below 65 ps are achieved based on a 0.18 µm digital-analog hybrid CMOS technology.
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表 1 DLL各模块噪声特性
噪声模块 传递函数 噪声特性 输入参考时钟 $\scriptsize{\varphi _{{\rm{n ,out}}}^2 = \varphi _{{\rm{n ,in}}}^2}$ 全通 鉴相器+电荷泵 $\scriptsize{\varphi _{{\rm{n ,out}}}^2 = {\left| {\dfrac{{{H_{\rm{O}}}(s)}}{{1 + {H_{\rm{O}}}(s)}}} \right|^2}\varphi _{{\rm{n,PD + CP}}}^2}$ 低通，带内平坦，带外衰减 环路滤波器 $\scriptsize{\varphi _{{\rm{n ,out}}}^2 = {\left| {\dfrac{{{K_{{\rm{VCDL}}}}}}{{1 + {H_{\rm{O}}}(s)}}} \right|^2}\varphi _{{\rm{n,LPF}}}^2}$ 高通，带内衰减，带外平坦 压控延迟链 $\scriptsize{\varphi _{{\rm{n ,out}}}^2 = {\left| {\dfrac{1}{{1 + {H_{\rm{O}}}(s)}}} \right|^2}\varphi _{{\rm{n,VCDL}}}^2}$ 高通，带内衰减，带外平坦 
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表 2 64×64规模时钟网络后仿真延迟时间(ns)
叶节点编号 tt corner ss corner ff corner snfp corner fnsp corner 叶节点1 1.266 1.524 1.017 1.234 1.239 叶节点2 1.268 1.527 1.019 1.232 1.237 叶节点3 1.264 1.526 1.016 1.236 1.241 叶节点4 1.263 1.523 1.017 1.235 1.240 叶节点5 1.265 1.526 1.015 1.232 1.238
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表 4 测试与后仿真总结
性能参数 测试/后仿真结果 工艺(μm) 0.18 电源电压(V) 1.8 DLL锁定范围(MHz) 150～400 DLL功耗(mW) 8.2～30.9 锁定范围内RMS Jitter(ps) 1.8～2.4 锁定范围内相位噪声(dBc/Hz)@1 MHz –127.8～–132.1 锁定范围内静态相位误差(ps) 47～65 时钟树各节点后仿真延迟(ps) 1247～1253
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