基于FPGA的水平集图像分割算法加速器

刘野; 肖剑彪; 吴飞; 常亮; 周军

doi:10.11999/JEIT210012

基于FPGA的水平集图像分割算法加速器

doi: 10.11999/JEIT210012

电子科技大学成都 611731

基金项目: 国家自然科学基金委员会-中国工程物理研究院NSAF联合基金(U2030204)

详细信息

作者简介:
刘野：男，1991年生，博士生，研究方向为图像处理算法与芯片协同设计

肖剑彪：男，1998年生，硕士生，研究方向为智能感知专用处理芯片设计

吴飞：男，1997年生，硕士生，研究方向为神经网络硬件加速器设计

常亮：男，1989年生，副研究员，研究方向为存算一体化人工智能芯片设计

周军：男，1982年生，教授，研究方向为智能感知算法与芯片协同设计

通讯作者:
周军　zhouj@uestc.edu.cn

中图分类号: TN47
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出版历程
- 收稿日期: 2021-01-05
- 修回日期: 2021-04-16
- 网络出版日期: 2021-04-29
- 刊出日期: 2021-06-18

A Fast and Efficient FPGA-based Level Set Hardware Accelerator for Image Segmentation

University of Electronic Science and Technology of China, Chengdu 611731, China

Funds: NSAF (U2030204)

摘要

摘要: 水平集算法因其出色的性能，在图像分割领域中得到了广泛的应用。同时，与基于深度学习的图像分割算法相比，水平集算法不需要训练数据，大幅降低了数据标记带来的工作量。然而，目前水平集算法主要是基于软件开发，涉及大量复杂的计算，以及计算的多次迭代，导致较高的处理延时与功耗。为了加快水平集算法的处理速度和降低功耗，该文提出了一种基于FPGA的水平集图像分割算法加速器，其中包含4个设计创新点：任务级并行处理、图像分块像素级并行处理、全流水线处理架构、分时复用的梯度和散度算子处理。实验结果表明，与在CPU上执行的水平集算法相比，该文提出的硬件加速器处理速度提升10.7倍，功耗仅为2.2 W。
- FPGA /
- 硬件加速器 /
- 水平集 /
- 图像分割
Abstract: The level set algorithm is widely used for image segmentation due to its high accuracy. In addition, compared to the deep learning-based image segmentation methods, the level set algorithm can be implemented without training data, which reduces significantly the labeling efforts. However, the normal level set algorithm is still developed using software, involving complex computation with a large number of pixels and iterations andcausing long processing time and large power consumption. In this work, an FPGA-based level set hardware accelerator is proposed for image segmentation. The proposed hardware accelerator contains four design components: task-level parallel processing, image splitting processing, fully-pipelined processing architecture, and time-multiplexed gradient and divergence processing engine. Based on the experimental results, the proposed hardware accelerator achieves up to 10.7 times acceleration compared to the level set algorithm executing on the CPU, with only 2.2 W power consumption.
- FPGA /
- Hardware accelerator /
- Level set /
- Image segmentation

HTML全文

图 1 水平集算法处理流程

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图 2 基于FPGA的水平集图像分割算法硬件架构

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图 3 任务级并行处理架构

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图 4 图像分块处理架构

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图 5 本文所提全流水线处理架构

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图 6 分时复用控制器以及时序图

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图 7 实验平台建立和实时演示平台

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图 8 软件和FPGA实现的分割结果对比

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图 9 分割时间对比

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图 10 硬件加速器分割结果轮廓及参考轮廓

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图 11 水平集硬件加速器功耗占比

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表 1 资源利用率

FPGA型号时钟频率 (MHz) Regs LUT DSP

Virtex7 100 40655(6.69%) 30680(10.10%) 307(10.96%)

下载: 导出CSV

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