基于施密特触发的高鲁棒性亚阈值标准单元

张跃军; 韩金亮; 张会红

doi:10.11999/JEIT210001

基于施密特触发的高鲁棒性亚阈值标准单元

doi: 10.11999/JEIT210001

张跃军^{1, 2},
韩金亮²,
张会红^2, ,

1.
复旦大学专用集成电路与系统国家重点实验室上海 201210
2.
宁波大学信息科学与工程学院宁波 315211

基金项目: 国家自然科学基金(61871244, 61874078)，专用集成电路与系统国家重点实验室开放研究课题基(2019KF002)，宁波市公益性计划项目(202002N3134)，宁波市自然科学基金(202003N4107)

详细信息

作者简介:
张跃军：男，1982年生，副教授，研究方向为低功耗、高信息密度集成电路理论和设计、安全芯片理论和设计

韩金亮：男，1996年生，硕士生，研究方向为低功耗集成电路设计

张会红：女，1976年生，副教授，研究方向为控制理论与应用、低功耗集成电路理论与优化设计

通讯作者:
张会红 zhanghuihong@nbu.edu.cn

中图分类号: TN492
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- 被引次数: 0
出版历程
- 收稿日期: 2021-01-04
- 修回日期: 2021-04-17
- 网络出版日期: 2021-04-30
- 刊出日期: 2021-06-18

High-Robust Sub-threshold Standard Cells Using Schmitt Trigger

1.
State Key Laboratory of Application Specific Integrated Circuits and Systems, Shanghai 201210, China
2.
Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo 315211, China

Funds: The National Natural Science Foundation of China (61871244, 61874078), The Open Research Project Fund of the State Key Laboratory of AISC and Systems (2019KF002), The S&T Plan of Ningbo Science and Technology Department (202002N3134), The Ningbo Natural Science Foundation (202003N4107)

摘要

摘要: 亚阈值电路是低功耗重要发展方向之一。随着电源电压降低，晶圆代工厂提供的标准单元电路性能容易受噪声和工艺偏差的影响，已经成为制约亚阈值芯片的瓶颈。该文提出一种基于施密特触发(ST)与反向窄宽度效应(INWE)的亚阈值标准单元设计方案。该方案首先利用ST的迟滞效应与反馈机制，在电路堆叠结点处添加施密特反馈管以优化逻辑门、减少漏电流、增强鲁棒性；然后，采用INWE最小宽度尺寸与分指版图设计方法，提高电路的开关阈值与MOS管的驱动电流；最后，在TSMC 65 nm工艺下构建标准单元的物理库、逻辑库和时序库，完成测试验证。实验结果表明，所设计的亚阈值标准单元与文献相比，功耗降低7.2%～15.6%，噪声容限提升11.5%～15.3%，ISCAS测试电路的平均功耗降低15.8%。
- 标准单元 /
- 低功耗 /
- 亚阈值 /
- 施密特触发特性
Abstract: Sub-threshold circuit is an important development direction of low power consumption. With the reduction of power supply voltage, the performance of standard cell circuits provided by foundries is susceptible to noise and process deviations, which has become a bottleneck restricting sub-threshold chips. The high-robust sub-threshold standard cells are proposed in this work. The Schmitt Trigger (ST) and Inverse Narrow Width Effect (INWE) are used to improve the performance, leakage, robust of the logic gates. Then, the INWE minimum width size and finger layout methods are used to increase the switching threshold of the circuit and the drive current of transistor. Finally, the standard cell library is designed and verified with TSMC 65 nm process. The experimental results show that the power of designed standard cells is reduced about 7.2%～15.6%, the noise margin is improved about 11.5%～15.3%, and the average power of ISCAS test circuit is reduced about 15.8%.
- Standard cell /
- Low power /
- Sub-threshold /
- Schmitt Trigger (ST)

HTML全文

图 1 6T施密特触发器及其泄漏路径

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图 2 6T施密特触发器的VTC曲线和开关电流比率

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图 3 施密特触发逻辑门

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图 4 半堆叠式ST亚阈值逻辑门

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图 5 NAND电路版图

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图 6 NOR电路版图

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图 7 SNM测试电路与蝶形图

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图 8 不同逻辑单元的静态噪声容限

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图 9 改进的ST电路与标准单元的延时、漏流、PDP及面积的对比

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表 1 基准测试电路验证与对比

基准测试电路	面积(µm²)		单元数量		功耗(mW)		延时(nS)
基准测试电路	Cov_lib	本文	Cov_lib	本文	Cov_lib	本文	Cov_lib	本文
c432	301	447	139	148	1.20E-02	1.01E-02	28.20	27.18
c499	571	742	193	180	3.48E-02	3.20E-02	23.01	21.53
c880	623	869	240	259	2.24E-02	1.86E-02	25.07	22.40
c3540	1942	2641	768	795	7.21E-02	6.10E-02	37.23	32.40
c7552	3193	3726	1246	1161	1.65E-01	1.26E-01	38.81	37.01

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