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基于差分传输管预充电逻辑的功耗恒定性电路改进设计

姚茂群 李聪辉

姚茂群, 李聪辉. 基于差分传输管预充电逻辑的功耗恒定性电路改进设计[J]. 电子与信息学报, 2021, 43(7): 1834-1840. doi: 10.11999/JEIT200513
引用本文: 姚茂群, 李聪辉. 基于差分传输管预充电逻辑的功耗恒定性电路改进设计[J]. 电子与信息学报, 2021, 43(7): 1834-1840. doi: 10.11999/JEIT200513
Maoqun YAO, Conghui LI. Improved Design of Constant Power Consumption Circuit Based on Differential Pass-transistor Precharge Logic[J]. Journal of Electronics & Information Technology, 2021, 43(7): 1834-1840. doi: 10.11999/JEIT200513
Citation: Maoqun YAO, Conghui LI. Improved Design of Constant Power Consumption Circuit Based on Differential Pass-transistor Precharge Logic[J]. Journal of Electronics & Information Technology, 2021, 43(7): 1834-1840. doi: 10.11999/JEIT200513

基于差分传输管预充电逻辑的功耗恒定性电路改进设计

doi: 10.11999/JEIT200513
基金项目: 国家自然科学基金(61771179),浙江省自然科学基金(LY15F010011)
详细信息
    作者简介:

    姚茂群:女,1967年生,教授,研究方向为低功耗数字集成电路设计、智能控制、神经网络和模糊逻辑、物联网及应用

    李聪辉:男,1996年生,硕士生,研究方向为低功耗数字集成电路设计、硬件安全

    通讯作者:

    姚茂群 yaomaoqun@163.com

  • 中图分类号: TN791

Improved Design of Constant Power Consumption Circuit Based on Differential Pass-transistor Precharge Logic

Funds: The National Natural Science Foundation of China (61771179), Zhejiang Provincial Natural Science Foundation (LY15F010011)
  • 摘要: 通过分析差分传输管预充电逻辑(DP2L)的电路结构,发现该电路还无法达到完全的功耗恒定特性,仍然存在被功耗攻击的风险。针对该问题,该文对DP2L的电路结构进行改进,并用Hspice对改进前后的电路进行模拟仿真测试。实验表明:改进后的DP2L电路结构具有更好的功耗恒定特性,更能满足该逻辑电路的设计要求。
  • 图  1  DP2L单轨输出“或”逻辑

    图  2  DP2L双轨输出“或”逻辑的构成

    图  3  4种输入信号下的DP2L单轨输出“或”逻辑瞬态电流曲线

    图  4  改进后DP2L单轨输出“或”逻辑

    图  5  4种输入信号下的改进后DP2L单轨输出“或”逻辑瞬态电流曲线

    图  6  4种输入信号下改进后DP2L双轨输出“或”逻辑瞬态电流曲线

    表  1  改进前DP2L单轨电路相关参数

    输入条件$a$=0, $b$=0$a$=0, $b$=1$a$=1, $b$=0$a$=1, $b$=1
    “0→1”翻转电流(μA)/48.8687.8262.12
    “1→0”翻转电流(μA)/58.1738.7597.74
    NED(%)33.05
    下载: 导出CSV

    表  2  改进后DP2L单轨电路相关参数

    输入条件$a$=0, $b$=0$a$=0, $b$=1$a$=1, $b$=0$a$=1, $b$=1
    “0→1”翻转电流(μA)/108.32107.65140.18
    “1→0”翻转电流(μA)/97.9698.31136.58
    NED(%)25.58
    下载: 导出CSV

    表  3  改进后DP2L双轨电路相关参数

    输入条件$a$=0, $b$=0$a$=0, $b$=1$a$=1, $b$=0$a$=1, $b$=1
    “0→1”翻转电流(μA)139.12139.01139.67139.51
    “1→0”翻转电流(μA)136.73136.51136.95136.82
    NED(%)0.40
    下载: 导出CSV

    表  4  同类型逻辑实现的“或”门标准化能量偏差对比

    逻辑电路WDDL改进前DP2L双轨电路LBDL改进后DP2L双轨电路
    NED(%)11.505.363.230.40
    下载: 导出CSV
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出版历程
  • 收稿日期:  2020-06-23
  • 修回日期:  2020-12-03
  • 网络出版日期:  2020-12-21
  • 刊出日期:  2021-07-10

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