A Low-Cost Triple-Node-Upset-Resilient Latch Design
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摘要: 随着集成电路特征尺寸的不断缩减，在恶劣辐射环境下，纳米级CMOS集成电路中单粒子三点翻转的几率日益增高，严重影响可靠性。为了实现单粒子三点翻转自恢复，该文提出一种低开销的三点翻转自恢复锁存器(LC-TNURL)。该锁存器由7个C单元和7个钟控C单元组成，具有对称的环状交叉互锁结构。利用C单元的阻塞特性和交叉互锁连接方式，任意3个内部节点发生翻转后，瞬态脉冲在锁存器内部传播，经过C单元多级阻塞后会逐级消失，确保LC-TNURL锁存器能够自行恢复到正确逻辑状态。详细的HSPICE仿真表明，与其他三点翻转加固锁存器(TNU-Latch, LCTNUT, TNUTL, TNURL)相比，LC-TNURL锁存器的功耗平均降低了31.9%，延迟平均降低了87.8%，功耗延迟积平均降低了92.3%，面积开销平均增加了15.4%。相对于参考文献中提出的锁存器，LC-TNURL锁存器的PVT波动敏感性最低，具有较高的可靠性。Abstract: As the feature size of integrated circuits continues to scale down, under the harsh radiation environment, the probability of single event triple node upsets in nano-scale CMOS integrated circuits is increasing, seriously affecting reliability. In order to realize the resilient of single-event triple-node-upsets, a Low-Cost Triple-Node-Upset-Resilient Latch (LC-TNURL) is proposed. The latch is composed of seven C-elements and seven clock-gating C-elements, and has a symmetrical ring-shaped cross-interlock structure. Using the interceptive characteristics of the C-elements and the cross-interlock connection mode, after any three internal nodes are flipped, the transient pulse propagates inside the latch. After the C-elements is blocked in multiple stages, it will disappear step by step to ensure the LC-TNURL latch can self-recover to the correct logic state. Detailed HSPICE simulation shows that the power consumption of the LC-TNURL latch is reduced by an average of 31.9%, the delay is reduced by an average of 87.8%, the power-delay product is reduced by an average of 92.3% and the area overhead is increased by an average of 15.4% compared to other triple-node-upsets hardened latches (TNU-Latch, LCTNUT, TNUTL, TNURL). The LC-TNURL latch proposed in this paper is the least sensitive to PVT fluctuations and has high reliability compared with reference latches.
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Key words:
- Latch /
- Radiation hardening by design /
- C-elements /
- Resilient /
- Triple node upsets
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