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用于全同态加密的数论变换乘法蝶形运算优化及实现

华斯亮 张惠国 王书昶

华斯亮, 张惠国, 王书昶. 用于全同态加密的数论变换乘法蝶形运算优化及实现[J]. 电子与信息学报, 2021, 43(5): 1381-1388. doi: 10.11999/JEIT200174
引用本文: 华斯亮, 张惠国, 王书昶. 用于全同态加密的数论变换乘法蝶形运算优化及实现[J]. 电子与信息学报, 2021, 43(5): 1381-1388. doi: 10.11999/JEIT200174
Siliang HUA, Huiguo ZHANG, Shuchang WANG. Optimization and Implementation of Number Theoretical Transform Multiplier Butterfly Operation for Fully Homomorphic Encryption[J]. Journal of Electronics & Information Technology, 2021, 43(5): 1381-1388. doi: 10.11999/JEIT200174
Citation: Siliang HUA, Huiguo ZHANG, Shuchang WANG. Optimization and Implementation of Number Theoretical Transform Multiplier Butterfly Operation for Fully Homomorphic Encryption[J]. Journal of Electronics & Information Technology, 2021, 43(5): 1381-1388. doi: 10.11999/JEIT200174

用于全同态加密的数论变换乘法蝶形运算优化及实现

doi: 10.11999/JEIT200174
基金项目: 江苏省自然科学基金(BK20191027)
详细信息
    作者简介:

    华斯亮:男,1981年生,副研究员,研究方向为专用集成电路设计、高性能计算

    张惠国:男,1978年生,副教授,研究方向为集成电路设计、功率电子技术

    王书昶:男,1985年生,讲师,研究方向为半导体光电子材料与器件

    通讯作者:

    华斯亮 huasiliang@cslg.edu.cn

  • 中图分类号: TN918.91; TN492

Optimization and Implementation of Number Theoretical Transform Multiplier Butterfly Operation for Fully Homomorphic Encryption

Funds: The Natural Science Foundation of Jiangsu Province (BK20191027)
  • 摘要: 全同态加密(FHE)可以真正从根本上解决云计算时将数据及其操作委托给第三方时的数据安全问题。针对全同态加密中占较大比例的大整数乘法运算优化需求,该文提出一种数论变换乘法蝶形运算的操作数合并算法,利用取模操作的快速算法,分别可将基16和基32运算单元的操作数减少到43.8%和39.1%。在此基础上,设计并实现了数论变换基32运算单元的硬件设计架构,在SMIC 90 nm工艺下的综合结果显示,电路的最高工作频率为600 MHz,面积1.714 mm2。实验结果表明,该优化算法提升了数论变换乘法蝶形运算的计算效率。
  • 图  1  输入数据$ {x}_{n} $的分割

    图  2  合并后$ {X}_{1} $的操作数

    图  3  合并后$ {X}_{2} $的操作数

    图  4  数论变换基32运算单元的硬件框图

    图  5  输入操作数的模加模块

    表  1  操作数合并算法

     输入:原始输入数据$ x $
     输出:合并后的操作数$ {\rm{OP}} $
      {//For $ {X}_{1} $ to $ {X}_{31} $ NTT output}
      for $ i=0 $ to 4 do
       for $ j=0 $ to $ 16/{2}^{i}-1 $ do
        $ k\leftarrow {2}^{i}\times \left(2j+1\right) $ {//For $ {\rm{OP}}\left[k\right] $ of $ k $-th NTT output}
        for $ \delta =0 $ to $ {2}^{i}-1 $ do
        for $ \beta =0 $ to CEILING($ 11/{2}^{i}-1 $) do
         $ n\leftarrow \delta \times $CEILING($ 11/{2}^{i}+\beta $) {//For $ {\rm{OP}}\left[k\right]\left[n\right] $}
         $ {\rm{OP}}\left[k\right]\left[n\right]\leftarrow {192'}{\rm{b}}0 $
         for $ \gamma =0 $ to $ 32/{2}^{i}-1 $ do
          for $ \alpha =0 $ to $ {2}^{i}-1 $ do
           $ m\leftarrow {2}^{i}\times \beta +\alpha $
           if $ m\ge 11 $ then
            PASS
           else
            $ {\rm{OP}}\left[k\right]\left[n\right][6\left(m+\gamma k\right)+5\left({\rm{mod}}\;192\right):$
            $6\left(m+\gamma k\right) \left({\rm{mod}}\;192\right)]\leftarrow x\left[6m+5:6m\right] $
           end if
          end for
         end for
        end for
       end for
      end for
     end for
     {//For $ {X}_{0} $ NTT output}
     for $ n=0 $ to 31 do
      $ {\rm{OP}}\left[0\right]\left[n\right]\leftarrow {96'}{\rm{b}}0 $
      $ {\rm{OP}}\left[0\right]\left[n\right]\left[63:0\right]\leftarrow x\left[n\right] $
     end for
    下载: 导出CSV

    表  2  基32运算单元的操作数

    数论变换输出个数合并前操
    作数数量
    合并后操
    作数数量
    $ {X}_{0} $13232
    奇数输出163211
    $ {X}_{8},{X}_{16},{X}_{24} $33216
    除$ {X}_{0},{X}_{8},{X}_{16},{X}_{24} $以外的偶数输出123212
    合计321024400
    下载: 导出CSV

    表  3  实现结果对比

    操作数总和最大频率(MHz)
    基16基32ASIC (@90 nm)FPGA
    文献[11]256200229.4 (@Altera Stratix V)
    文献[14]102498.02 (@Altera Stratix V)
    本文112400600320 (@Xilinx Kintex UltraScale)
    操作数减少(%)43.839.1
    下载: 导出CSV
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  • 被引次数: 0
出版历程
  • 收稿日期:  2020-03-17
  • 修回日期:  2020-10-21
  • 网络出版日期:  2020-11-19
  • 刊出日期:  2021-05-18

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