Memristive Digital Logic Circuit Design
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摘要: 该文简要概述了忆阻器理论的提出、应用现状及其在电子技术领域发展的现状，介绍了忆阻器在数字逻辑电路设计中的重要意义，并结合惠普(HP)忆阻器的二值特性及其电路特性，对忆阻器在数字逻辑电路设计中的发展、趋势及可应用前景进行了综述，可为忆阻器在数字逻辑电路中的后续研究及相关应用提供一定的参考。Abstract: A brief overview of the theory of memristor, the state of applied research and its current status in the field of electronic technology are proposed. The importance of memristor in the design of digital logic circuits is also introduced. Combined with the binary characteristics and circuit characteristics of Hewlett Packard(HP) memristor, the development status, trend and applicable prospects of memristor in digital logic circuit design are reviewed, which provide certain reference for further research based on memristor in digital logic circuit design and other related applications.
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Key words:
- Memristor /
- Digital logic circuit /
- Binary characteristic
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1. 引言
忆阻器是一种具有记忆特性和非线性特性的新型电路元件，是与传统电路元件中的电阻、电容和电感相并列第4类基本电路元件。1971年，基于对称性原理，文献[1]中首次预测了忆阻器的存在，并指出“基于电路理论和准静态电磁分析理论，忆阻器的存在不是凭空想象，而是有据可查的”。但由于当时并没有实际的忆阻器被发现，导致这一理论没有得到广泛关注。直到2008年惠普(Hewlett-Packard, HP)忆阻器的成功制备[2]，首次将忆阻器这一理论概念与实际的物理器件实现关联，证实了这一预测的有效性。同时，在真正意义上开启了世界范围内对忆阻器的研究热潮。近年来，HP忆阻器凭借其非易失性、突触特性及纳米尺度等优势，在非易失性存储器、神经网络、大规模集成电路及非线性电路等诸多领域显现出巨大的应用潜力[3-6]。
忆阻器非易失性及纳米尺度的特点，为其在存储方面的应用提供了独特的优势潜能，使其完全有可能在下一代低功耗、高密度存储系统中扮演起领军角色[7-10]；而其优良的突触模拟特性，使得忆阻器可以作为模仿、记忆和学习的基本模块。早在2014年，文献[11]就有提出分布在神经元轴突整个长度上的钾离子通道和钠离子通道实为局部有源忆阻器。然而，忆阻器值得引起人们关注的绝不仅仅局限于此，忆阻器提供了一种非传统的计算架构，即将信息存储和处理组合在一起，完全区别于当今的主流计算技术，且有助于解决目前流行的计算范式无法有效地应对现代新兴的应用程序必须处理越来越大的数据量这一问题，可以说基于忆阻器的数字逻辑电路为探索先进计算机架构开辟了新的道路[12,13]。而此方面研究的展开，主要得益于HP忆阻器的二值特性。
由于HP忆阻器的二值特性是忆阻器在数字逻辑电路中得以应用的重要基础，本文首先对HP忆阻器的二值特性及其电路特性进行了回顾，并在此基础上，总结概括出两类忆阻器数字逻辑电路；其次，详尽地介绍了忆阻器数字逻辑电路理论发展及应用现状；最后，对忆阻器在数字逻辑电路中的现状进行了总结，并对其应用前景进行了展望。
2. HP忆阻器二值特性及其电路特性
HP忆阻器的二值特性也称为阈值特性，即纳米尺度的HP忆阻器，在外电场的作用下，其内部掺杂区与非掺杂区的分界面(以下简称“分界面”)会迅速漂移至其两极中的某一极，从而使其呈现出对应的两个极值阻态：高阻态(ROFF)、低阻态(RON)。在忆阻器存储和逻辑电路应用方面，大多利用HP忆阻器的这一特性。
HP忆阻器的结构呈图1(a)所示的三明治结构，将1块纳米级的二氧化钛(TiO2)夹在两个铂(Pt)电极中间，通过对其中的1/2进行“掺杂”形成了含有一定氧空穴的TiO2-x掺杂区。根据HP忆阻器的电路特性可知，掺杂区一侧为HP忆阻器的“正极”，非掺杂区一侧为HP忆阻器“负极”。因此，当给HP忆阻器施加正向电压时，如图1(b)所示，其分界面将向负极移动，导致其掺杂区的宽度W1趋近整个忆阻器长度D，使得忆阻器等效电阻为RON。反之，当施加反向电压时，如图1(c)所示，分界面在外加电场的作用下向忆阻器的正极移动，使非掺杂层的宽度W2增大致接近D，此时，忆阻器的等效电阻达到ROFF。
依据上述HP忆阻器的二值特性，在实际的电路中，通过施加不同方向的外加电场于HP忆阻器两端，即可实现忆阻器阻态在RON和ROFF间的切换，如当给HP忆阻器两端施加零偏置的周期性激励信号时，可测量得到忆阻器的v-i特性曲线具有两种不同的斜率。以输入信号为正弦信号v=0.4sin(πt)为例，通过MATLAB仿真可得到如图2所示的v-i特性曲线，当施加正向电压且达到正向阈值电压时，忆阻器的阻态将从ROFF切换为RON，而当对忆阻器施加反向电压且达到其反向阈值电压时，忆阻器的阻态将从RON转换为ROFF。
基于忆阻器的数字逻辑电路，根据其逻辑状态变量的不同可将其分别两类，一类是以忆阻器的忆阻值作为逻辑运算的操作数，如忆阻实质蕴涵逻辑电路(material IMPLication, IMPLY)和忆阻器辅助逻辑电路(Memristor-Aided loGIC, MAGIC)；另一类是以电压量作为操作数的忆阻数字逻辑电路，如忆阻器比例逻辑(Memristor Ratioed Logic, MRL)。但无论是上述哪一类忆阻数字逻辑电路，其电路功能的实现均需遵循HP忆阻器的上述二值特性。
3. 忆阻器数字逻辑电路
按照忆阻器逻辑电路发展的时间顺序，本文对由忆阻器构成的实质蕴涵逻辑电路(IMPLY)、忆阻器/CMOS混合逻辑电路、忆阻器辅助逻辑电路(MAGIC)、CMOS /忆阻器阈值逻辑、类CMOS忆阻器互补逻辑以及并行输入处理忆阻器逻辑等进行主要介绍。此外，对忆阻器在其它数字逻辑电路中的相关应用，也予以综述介绍。
3.1 忆阻实质蕴涵逻辑电路
实质蕴涵逻辑由怀海德和罗素于1910年构建，是4种基本逻辑运算之一[14]，其真值表如图3(a)所示。2008年，HP实验室发现通过一种简单的电路结构就可以实现基于忆阻器的实质蕴涵逻辑的计算[15-16]，电路结构如图3(b)所示。在该电路中使用了P, Q两个相同参数的忆阻器和两个三态电压驱动器，其中三态电压驱动器用以提供实现运算所必需的VCOND和VSET两种电压，并可以在不需要驱动的情况下呈现高阻态。在该电路中使用忆阻器的阻值作为逻辑状态变量，高阻值ROFF表示逻辑“0”，低阻值RON表示逻辑“1”。电路将P, Q两个忆阻器的初始状态作为输入，忆阻器Q的次态作为输出。实际上，忆阻实质蕴涵逻辑电路更重要的研究意义在于，通过拓展该电路的结构可实现基本的布尔逻辑运算。如图4所示，应用图4(a)所示的结构以及图4(b)所展示的过程，通过多步实质蕴涵逻辑运算即可实现基本逻辑“或”运算。
2012年，文献[17]提出了3种忆阻实质蕴涵逻辑新的综合方法，并与在文献[16]中所提出的方法进行了比较。结果表明，通过使用变量的互补表示和多输入操作，可以极大地减少计算给定布尔函数所需的计算序列的长度，其所提出的NAND-OR方法最多需要2n-1+1个步骤即可完成给定的n输入布尔逻辑。文献[18]中提出了一种CMOS/忆阻器电路架构用以完成实质蕴涵逻辑的计算，以减少计算序列长度并实现并行运算。文献[19]介绍了在CMOS/分子(CMOS/MOLecular, CMOL)架构上实现基于实质蕴涵逻辑的“或非”门设计。文献[20]提出了一组使用互补电阻开关(Complementary Resistive Switch, CRS)通过实质蕴涵逻辑实现基本逻辑功能的方法，并将其扩展至8位加法器和4位乘法器的算术电路。文献[21]提出了一种基于纳米交叉开关的结构，用于完善忆阻实质蕴涵逻辑中忆阻器不能达到最小电阻值的限制。文献[22]提出了一种基于实质蕴涵的“或非”门的FPGA体系结构，在该结构中使用忆阻器实现逻辑功能，并使用嵌入式存储器存储数据。文献[23,24]中介绍了基于实质蕴涵逻辑的忆阻器驱动门(Memristors-As-Drivers Gate, MAD Gate)，并指出MAD门对于任何布尔逻辑运算都可将延迟减少到单个步骤，同时可将每个门的实现减少到最多使用3个忆阻器，以达到减小器件面积的目的。文献[25]将忆阻实质蕴涵逻辑与电流镜结合在一起，可以解决蕴涵逻辑的受限扇出问题，从而使更多操作得以并行运行。
研究证明通过引入因式形式、多忆阻器蕴涵、乘积和以及多级进化算法等方法可以显著减少蕴涵逻辑的平均操作数[26-31]。同时基于忆阻器的实质蕴涵逻辑还被广泛用于加法器、线性反馈移位寄存器、多路分配器、编码器、解码器、幅度比较器、T触发器、计数器、乘法器、比较器等数字逻辑电路中[32-44]。
3.2 忆阻器/CMOS混合逻辑电路
为了能与现行的标准CMOS逻辑相兼容，文献[45]中提出了一种混合CMOS/忆阻逻辑概念，并将其称之为忆阻器比例逻辑 (Memristor Ratioed Logic, MRL)。MRL逻辑门的电路结构如图5所示，其中图5(a)为“或”门，图5(b)为“与”门。MRL“或”门和“与”门分别由两个极性相反的忆阻器串联组成，同时使用了CMOS反相器用于提供完整的逻辑门并恢复退化信号。在MRL逻辑门中使用电压作为逻辑状态变量，高电平为逻辑“1”，低电平为逻辑“0”。MRL逻辑门的输入为每个忆阻器的浮动端口，输出则为连接两个忆阻器的公共节点。为了验证MRL逻辑门的可行性，文中设计了一个8位全加器作为案例进行研究。研究表明：(1)与传统的CMOS逻辑相比，使用MRL逻辑门节省了约50%的面积；(2)无电流阈值的线性忆阻器更适合应用于MRL逻辑，与使用非线性忆阻器的逻辑电路相比，基于线性忆阻器件的MRL逻辑门的速度更快、面积更小、功耗更低。
在文献[46,47]中提出了一种基于MRL逻辑的通用逻辑门，配合使用COMS反相器，该逻辑门将“与”门、“或”门和“异或”门的功能集成于一体，同时还设计了基于该通用逻辑门的2×2乘法器。文献[48]设计了基于MRL逻辑的“异或”门和“同或”门，该逻辑门能在一个时钟周期内以电压形式产生输出。此外，MRL逻辑门也被用于设计各种数字逻辑电路[49-51]。
3.3 忆阻器辅助逻辑电路
Kvatinsky等人[52]于2014年提出了一种新的忆阻逻辑方法——忆阻器辅助逻辑(Memristor Aided loGIC, MAGIC)。MAGIC逻辑门的电路构成如图6所示。MAGIC逻辑门仅由忆阻器简单连接构成且仅有一个控制电压，在简化了逻辑电路操作的同时，实现了降低电路的复杂性。在MAGIC逻辑门中使用忆阻器的阻值作为逻辑状态变量，将MIN忆阻器的阻值作为输入，MOUT忆阻器的阻值作为输出。与实质蕴涵逻辑不同，MAGIC逻辑中的输入和输出是分离的，并且输出被写入专用的输出忆阻器中。
如图6所示，MAGIC逻辑门的拓扑结构与常见的基于忆阻器的交叉开关存储阵列的结构类似，因此，将其应用于存储器中可同时实现数据的存储和逻辑计算，而这种特性恰恰有助于实现不同于传统的冯·诺依曼架构的新型计算机架构[53-63]。文献[64]对MAGIC逻辑门进行了扩展，扩展后的逻辑门(“或”逻辑门除外)不仅能用作独立的逻辑门，而且还可以在交叉开关阵列中得到应用。文献[65]提出了一种非理想的MAGIC“或非”门模型并进行了仿真，探讨了实际电路实现中可能出现的工艺变化和寄生效应产生的影响。此外，MAGIC逻辑门也被用于设计如二进制比较器等数字逻辑电路[66]。
3.4 CMOS /忆阻器阈值逻辑
阈值逻辑较布尔逻辑具有更强大的计算能力，高性能阈值逻辑电路的发展将有助于展开与计算机有关的重要应用。n输入线性阈值门(Linear Threshold Gate, LTG)的传递函数如式(1)所示
f(x1,x2,···,xn)={1, n∑i=1wixi≥T0, 其他 (1) 其中，xi是布尔输入变量，wi是第i个输入的整数权重，T是整数阈值。文献[67]研究了各种LTG的实现方式，指出目前大多数实现方式中权重wi都是固定值，难以对其数值进行更改，但忆阻器的电阻切换的特性恰恰能够较容易地实现对权重wi的改变。
文献[68]使用忆阻器实现了可编程阈值门，忆阻器的阻值作为阈值门的输入权重，通过更改忆阻器的忆阻值对阈值门进行编程，实现了不同的布尔函数。图7展示了一个3输入阈值门的电路结构，其中①是防止电流倒流的电流镜；②是防止负载的隔离器；③是保持输入脉冲周期的周期扩展器；④是保持忆阻值的脉冲整形器。文中还提出了一种基于上述忆阻器可编程阈值门的阈值门阵列架构，并通过对其功率、面积和延迟指标进行评估发现，与基于CMOS的查找表(Look-Up-Table, LUT) 相比，该忆阻阈值架构的功耗和有效面积减少了约75%，但与此同时也会带来一定的延时处罚。
文献[69]通过混合CMOS/忆阻器实现了一种可编程阈值逻辑门。一个4输入可编程阈值逻辑门的电路结构如图8(a)所示。图8(b)上的阴影区域显示了忆阻器可以用于实施阈值门的电阻状态的范围。在该逻辑门中，忆阻器用于实现比例二极管电阻逻辑，而CMOS电路则用于信号的放大以及反相，加之忆阻器件在该电路结构中可辅助实现了较好的缩放比例功能和非易失性模拟存储器特性，使得该阈值逻辑门可以很方便地实现现场配置。由于在逻辑操作过程中，忆阻器件的状态不会发生改变，使得这种实现方式更具有鲁棒性。文中还通过实验得到了一种由集成CMOS触发器、硅二极管和Ag/a-Si/Pt忆阻器件构成的4输入对称线性阈值门，进一步验证了该可编程阈值逻辑门的可行性。
文献[70]提出了用于忆阻器交叉开关的新型阈值门，以及一种新型的混合阈值-布尔逻辑设计方法，并用其设计了两个32位加法器(使用两个不同的一位全加法器作为基本单元)。研究者们还设计了许多种不同的改进型的忆阻CMOS阈值逻辑单元，并将其应用于FFT, Vedic乘法计算电路、加法器等应用中，能有效地减少功耗和片上面积[71-77]。
3.5 类CMOS忆阻器互补逻辑
Vourkas等人在文献[78]中提出了一种类CMOS的电路设计范式，用于创建忆阻互补逻辑电路。图9展示了布尔逻辑门的类COMS忆阻电路实现。电路中的忆阻器被显示为3端器件，以强调与CMOS对应器件的相似性。类CMOS忆阻器互补逻辑使用电压表示逻辑状态，输入信号用正电压表示逻辑“1”，负电压表示逻辑“0”。输出电压以接近VDD的电压值对应逻辑“1”，接近GND的则对应逻辑“0”。图10展示了基于类CMOS通用布尔逻辑门的半加器以及用于实现逻辑函数
F=(AB+CD)′ 的电路。在文献[79]中对类CMOS方法进行了改进。如图11所示为一个改进后的二输入类CMOS与非门，在该结构中忆阻器具有两端口特性，以及能在同时施加输入电压时适当隔离忆阻器组。该电路由忆阻器和一些辅助晶体管组成，其中，后者有助于在施加相同输入逻辑信号时对多个忆阻器进行正确的访问操作。在该逻辑门中有4个开关(三态电压驱动器M1-M4)，用于决定逻辑门的功能并能完成以下3种操作：(1)施加输入信号；(2)通过VDD和GND信号读取逻辑输出；(3)关闭电路[80]。
3.6 并行输入处理忆阻器逻辑
Papandroulidakis等人[81]提出了一种新型的忆阻逻辑概念，它能够并行执行数字逻辑运算，并有希望加速新一代的忆阻逻辑芯片的实现。图12(a)所示为6种二输入布尔逻辑门的结构，图12(b)所示为使用该忆阻逻辑门构建的计算电路。该逻辑门使用电压作为逻辑状态，0 V表示逻辑“0”，而逻辑“1”对应的电压介于已定义的开关阈值的第1个(较低)和第2个(较高)之间。值得注意的是在经过一次逻辑计算之后，逻辑门中的忆阻器需要有一个复位步骤，否则将会导致错误的输出。该电路结构中，负载电阻RL要求最好是一个小于RON的电阻，以保证其上面的压降较小，进而保证忆阻电路中的全部忆阻器不会在逻辑操作过程中产生误操作，从而可以准确地从该串联负载电阻RL中读出电路的输出。当逻辑门进行级联操作时，输出的电压值会逐级减少，因此，需要使用CMOS反相器以完成信号的恢复。
3.7 其它忆阻数字逻辑电路
除上述几种数字逻辑电路设计以外，忆阻器还被用于3值逻辑电路的设计之中。文献[82-88]利用忆阻器、CNTFET等实现了3值逻辑，包括与门、或门等基本逻辑门，以及3进制解码器、两位加法器、比较器、乘法器等更复杂的数字逻辑电路设计。与传统的2值逻辑相比，3值逻辑具有单根信号线的信息携带量更高，电路串并行运算能力更强，电路复杂度更低等优点。
在文献[89-93]中介绍了忆阻器在FPGA中的应用。由于忆阻器相比于MOS晶体管具有面积和功耗都更小的特点，因此，可以通过使用忆阻器来减小专用集成电路(Application Specific Integrated Circuit, ASIC)与FPGA之间的差距。文献[94,95]设计了基于CRS的状态逻辑运算电路。
3.8 小结
自HP实验室发现忆阻器可以用于逻辑运算并实现了基于忆阻器的实质蕴涵电路，研究者们陆续设计了诸多基于忆阻器的数字逻辑电路设计方案，并证明了基于忆阻器的数字逻辑电路相对于CMOS实现的数字逻辑电路，可以有效减少电路的面积和功耗。同时，研究者们还发现忆阻器交叉开关结构不仅可以完成逻辑运算还可以用于存储信息，这一特性使得忆阻器可以在存储器中完成逻辑运算，有助于实现不同于传统的冯·诺依曼架构的新型计算机架构。此外，由于忆阻器在不使用额外硬件的情况下可以处理两个以上的状态，因此，忆阻器也是实现3进制系统的一个很好的候选者[82]，这使得3值逻辑与忆阻器的结合成为了可能，也为3值及多值数字逻辑电路的设计提供了可能。独特的2值特性，使忆阻器能够在数字逻辑电路中扮演一个非常重要的角色，为未来数字逻辑电路的设计提供了更多的选择。
4. 结束语
忆阻器作为第4类电路元件，具有区别于传统电路元件电阻、电容和电感的显著特点，即非易失性，HP忆阻器作为首个忆阻器的物理实现，目前已被广泛应用于非易失性存储、大数据存储、可编程逻辑电路等领域；除了具有非易失性特点外，HP忆阻器纳米尺度特点使其在集成电路方面的应用也占据一定优势。而作为非线性电路元件，忆阻器在仿生及神经网络、非线性电路等方面也得到了广泛应用。自2008年，HP实验室将HP忆阻器应用于实质蕴涵逻辑开始，研究者们陆续提出了MRL, MAGIC, CMOS/忆阻器阈值逻辑、类CMOS忆阻器互补逻辑、并行输入处理忆阻器逻辑等。其中，忆阻器交叉开关在能存储数据的同时，还能通过运用以上所述的逻辑方案来实现逻辑运算。事实上，忆阻器在数字逻辑电路中的应用不只局限于本文所提及的各类电路，利用HP忆阻器的2值特性还可以用于实现3值逻辑以及更多值的逻辑。总之，忆阻器作为一种新型记忆元件，有着广泛的应用前景和研究空间，忆阻器的应用研究也必然会成为倍受瞩目的课题之一。
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