基于忆阻器的乘法器电路设计

王光义; 沈书航; 刘公致; 李付鹏

doi:10.11999/JEIT190811

基于忆阻器的乘法器电路设计

doi: 10.11999/JEIT190811

杭州电子科技大学现代电路与智能信息研究所杭州 310018

基金项目: 国家自然科学基金(61771176, 61801154)

详细信息

作者简介:
王光义：男，1957年生，教授，博士生导师，研究方向为非线性电路与系统

沈书航：男，1994年生，硕士生，研究方向为非线性电路与系统

刘公致：男，1971年生，副研究员，研究方向为非线性电路与系统

李付鹏：男，1986年生，助理实验师，研究方向为非线性电路与系统

通讯作者:
刘公致　hzlgz0@163.com

中图分类号: TN601; TN710
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- 被引次数: 0
出版历程
- 收稿日期: 2019-10-18
- 修回日期: 2020-01-19
- 网络出版日期: 2020-02-25
- 刊出日期: 2020-06-04

Design of Memristor Based Multiplier Circuits

Institute of Modern Circuits and Intelligent Information, Hangzhou Dianzi University, Hangzhou 310018, China

Funds: The National Natural Science Foundation of China (61771176, 61801154)

摘要

摘要: 忆阻器作为一种非易失性的新型电路元件，在数字逻辑电路中具有良好的应用前景。目前，基于忆阻器的逻辑电路主要涉及全加器、乘法器以及异或(XOR)和同或(XNOR)门等研究，其中对于忆阻乘法器的研究仍比较少。该文采用两种不同方式来设计基于忆阻器的2位二进制乘法器电路。一种是利用改进的“异或”及“与”多功能逻辑模块，设计了一个2位二进制乘法器电路，另一种是结合新型的比例逻辑，即由一个忆阻器和一个NMOS管构成的单元门电路设计了一个2位二进制乘法器。对于所设计的两种乘法器进行了比较，并通过LTSPICS仿真进行验证。该文所设计的乘法器仅使用了2个N型金属-氧化物-半导体(NMOS)以及18个忆阻器(另一种为6个NMOS和28个忆阻器)，相比于过去的忆阻乘法器，减少了大量晶体管的使用。
- 忆阻器 /
- 逻辑电路 /
- 乘法器
Abstract: As a new non-volatile electronic device, memristor has a good application prospect in digital logic circuits. At present, memristor based logic circuits mainly involve the research of full adder, multiplier, exclusive-OR (XOR) and equivalence (XNOR), etc., among which there is little research on memristor based multiplier. The 2-bit binary multiplier circuit is designed in two different ways based on memristor. One is to design a 2-bit binary multiplier circuit by using the improved XOR and AND multifunctional logic modules. The other is to design a 2-bit binary multiplier by combining a new type of ratio logic, i.e. a unit gate circuit consisting of one memristor and one NMOS transistor. The two multipliers are compared and validated by LTSPICS simulation. The multiplier designed in this paper only uses 2 N-Metal-Oxide-Semiconductor (NMOS) and 18 memristors (the other is 6 NMOS and 28 memristors). Compared with previous memristor based multipliers, the multipliers in this paper reduce the number of transistors.
- Memristor /
- Logic circuits /
- Multiplier

HTML全文

图 1 忆阻器的I-V 滞回曲线图

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图 2 忆阻器构建的“或”、“与”、“或非”、“与非”门

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图 3 基于忆阻器比例逻辑的新型基础逻辑电路

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图 4 “异或”及“与”多功能逻辑模块

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图 5 “异或”及“与”多功能逻辑模块仿真图

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图 6 2位二进制乘法器器框图和真值表

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图 7 基于新型比例逻辑的2位二进制乘法器

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图 8 基于多功能模块的2位二进制乘法器

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图 9 基于新比例逻辑的2位二进制乘法器仿真结果

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图 10 基于多功能模块的2位二进制乘法器仿真结果

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表 1 不同“异或门”之间的元器件使用数量比较

异或门
文献[16] 文献[13] 文献[14] 文献[15] 文献[20] 本文

晶体管数 4 3 1 2 2 1
忆阻器数 1 4 4 4 4 5
电阻数无无 1R 1R 无无

下载: 导出CSV

表 2 2位二进制乘法器元器件使用数量

乘法器
传统CMOS 文献[18] 文献[20] 新比例逻辑多功能模块

晶体管数 62 32 8 6 2
忆阻器数 – 34 16 30 18

下载: 导出CSV

参考文献(23)

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