Design of Memristor Based Multiplier Circuits
-
摘要: 忆阻器作为一种非易失性的新型电路元件，在数字逻辑电路中具有良好的应用前景。目前，基于忆阻器的逻辑电路主要涉及全加器、乘法器以及异或(XOR)和同或(XNOR)门等研究，其中对于忆阻乘法器的研究仍比较少。该文采用两种不同方式来设计基于忆阻器的2位二进制乘法器电路。一种是利用改进的“异或”及“与”多功能逻辑模块，设计了一个2位二进制乘法器电路，另一种是结合新型的比例逻辑，即由一个忆阻器和一个NMOS管构成的单元门电路设计了一个2位二进制乘法器。对于所设计的两种乘法器进行了比较，并通过LTSPICS仿真进行验证。该文所设计的乘法器仅使用了2个N型金属-氧化物-半导体(NMOS)以及18个忆阻器(另一种为6个NMOS和28个忆阻器)，相比于过去的忆阻乘法器，减少了大量晶体管的使用。Abstract: As a new non-volatile electronic device, memristor has a good application prospect in digital logic circuits. At present, memristor based logic circuits mainly involve the research of full adder, multiplier, exclusive-OR (XOR) and equivalence (XNOR), etc., among which there is little research on memristor based multiplier. The 2-bit binary multiplier circuit is designed in two different ways based on memristor. One is to design a 2-bit binary multiplier circuit by using the improved XOR and AND multifunctional logic modules. The other is to design a 2-bit binary multiplier by combining a new type of ratio logic, i.e. a unit gate circuit consisting of one memristor and one NMOS transistor. The two multipliers are compared and validated by LTSPICS simulation. The multiplier designed in this paper only uses 2 N-Metal-Oxide-Semiconductor (NMOS) and 18 memristors (the other is 6 NMOS and 28 memristors). Compared with previous memristor based multipliers, the multipliers in this paper reduce the number of transistors.
-
Key words:
- Memristor /
- Logic circuits /
- Multiplier
-
表 1 不同“异或门”之间的元器件使用数量比较
下载: 导出CSV
-
HARON N Z and HAMDIOUI S. Why is CMOS scaling coming to an end?[C]. The 3rd International Design and Test Workshop, Monastir, Tunisia, 2008: 98–103. doi: 10.1109/IDT.2008.4802475. CHUA L. Memristor-the missing circuit element[J]. IEEE Transactions on Circuit Theory, 1971, 18(5): 507–519. doi: 10.1109/TCT.1971.1083337 STRUKOV D B, SNIDER G S, STEWART D R, et al. The missing memristor found[J]. Nature, 2008, 453(7191): 80–83. doi: 10.1038/nature06932 KIM K H, GABA S, WHEELER D, et al. A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications[J]. Nano Letters, 2011, 12(1): 389–395. doi: 10.1021/nl203687n ZHENG Nan and MAZUMDER P. Learning in memristor crossbar-based spiking neural networks through modulation of weight-dependent spike-timing-dependent plasticity[J]. IEEE Transactions on Nanotechnology, 2018, 17(3): 520–532. doi: 10.1109/TNANO.2018.2821131 VOURKAS I and SIRAKOULIS G C. Emerging memristor-based logic circuit design approaches: A review[J]. IEEE Circuits and Systems Magazine, 2016, 16(3): 15–30. doi: 10.1109/MCAS.2016.2583673 曾以成, 成德武, 谭其威. 简洁无电感忆阻混沌电路及其特性[J]. 电子与信息学报, 2019, 42(4): 862–869. doi: 10.11999/JEIT190859ZENG Yicheng, CHENG Dewu, and TAN Qiwei. A simple inductor-free memristive chaotic circuit and its characteristics[J]. Journal of Electronics &Information Technology, 2019, 42(4): 862–869. doi: 10.11999/JEIT190859 沈怡然, 李付鹏, 王光义. 荷控忆阻器记忆衰退的寄生效应[J]. 电子与信息学报, 2020, 42(4): 844–850. doi: 10.11999/JEIT190865SHEN Yiran, LI Fupeng, and WANG Guangyi. The role of parasitic elements in fading memory of a charge controlled memristor[J]. Journal of Electronics &Information Technology, 2020, 42(4): 844–850. doi: 10.11999/JEIT190865 KVATINSKY S, BELOUSOV D, LIMAN S, et al. MAGIC—Memristor-aided logic[J]. IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, 2014, 61(11): 895–899. doi: 10.1109/TCSII.2014.2357292 WANG H P, LIN C C, WU C C, et al. On synthesizing memristor-based logic circuits with minimal operational pulses[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018, 26(12): 2842–2852. doi: 10.1109/TVLSI.2018.2816023 KVATINSKY S, WALD N, SATAT G, et al. MRL—Memristor ratioed logic[C]. The 13th International Workshop on Cellular Nanoscale Networks and their Applications, Turin, Italy, 2012: 1–6. doi: 10.1109/CNNA.2012.6331426. XIE Lei, DU N H A, TAOUIL M, et al. A mapping methodology of boolean logic circuits on memristor crossbar[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, 37(2): 311–323. doi: 10.1109/TCAD.2017.2695880 XU Xiaoyan, CUI Xiaole, LUO Mengying, et al. Design of hybrid memristor-MOS XOR and XNOR logic gates[C]. 2017 International Conference on Electron Devices and Solid-State Circuits, Hsinchu, China, 2017: 1–2. doi: 10.1109/EDSSC.2017.8126414. YANG Xiaohan, ADEYEMO A, BALA A, et al. Novel memristive logic architectures[C]. The 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, Bremen, Germany, 2016: 196–199. doi: 10.1109/PATMOS.2016.7833687. WANG Xiaoping, YANG Ran, CHEN Qiao, et al. An improved memristor-CMOS XOR logic gate and a novel full adder[C]. The 9th International Conference on Advanced Computational Intelligence, Doha, Qatar, 2017: 7–11. doi: 10.1109/ICACI.2017.7974477. ZHOU Yaxiong, LI Yi, XU Lei, et al. A hybrid memristor‐CMOS XOR gate for nonvolatile logic computation[J]. Physica Status Solidi (A) , 2016, 213(4): 1050–1054. doi: 10.1002/pssa.201532872 SINGH A. Memristor based XNOR for high speed area efficient 1-bit full adder[C]. 2017 International Conference on Computing, Communication and Automation, Greater Noida, India, 2017: 1549–1553. doi: 10.1109/CCAA.2017.8230048. SINGH T. Hybrid memristor-cmos (memos) based logic gates and adder circuits[J]. arXiv: 1506.06735, 2015. LIU Gongzhi, ZHENG Lijing, WANG Guangyi, et al. A carry lookahead adder based on hybrid CMOS-memristor logic circuit[J]. IEEE Access, 2019, 7: 43691–43696. doi: 10.1109/ACCESS.2019.2907976 TEIMOORY M, AMIRSOLEIMANI A, AHMADI A, et al. A hybrid memristor-CMOS multiplier design based on memristive universal logic gates[C]. The 60th IEEE International Midwest Symposium on Circuits and Systems, Boston, USA, 2017: 1422–1425. doi: 10.1109/MWSCAS.2017.8053199. SHIN S, KIM K, and KANG S M. Memristive XOR for resistive multiplier[J]. Electronics Letters, 2012, 48(2): 78–80. doi: 10.1049/el.2011.3270 YAKOPCIC C, TAHA T M, SUBRAMANYAM G, et al. Generalized memristive device SPICE model and its application in circuit design[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013, 32(8): 1201–1214. doi: 10.1109/TCAD.2013.2252057 SINGH A. Design and analysis of memristor-based combinational circuits[J]. IETE Journal of Research, 2018, 33(4): 1–10. doi: 10.1080/03772063.2018.1486741 -
图(10) / 表(2)
计量
- 文章访问数: 3911
- HTML全文浏览量: 1261
- PDF下载量: 255
- 被引次数: 0
下载:
