Optimization Algorithm of Dual-port Memory Mapping on FPGA
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摘要: FPGA存储器映射算法负责将用户的逻辑存储需求映射到芯片中的分布式存储资源上实现。前人对双端口存储器的映射算法研究相对较少，成熟的商业EDA工具的映射结果仍有不少改进空间。该文分别针对面积、延时、功耗这3个常用指标，提出一种双端口存储器映射的优化算法，并给出了具体配置方案。实验表明，在面向简单存储需求时，与商用工具Vivado的映射结果一致；在面向复杂存储需求时，面积优化和功耗优化的映射结果对比商用工具改善了至少50%。Abstract: FPGA memory mapping algorithm utilizes distributed storage resources on chip and cooperates with some auxiliary circuits to realize the different needs of users in designing logical storage functions. Previous studies on dual-port memory mapping algorithm are relatively few. There is still much space for improvement in the mapping results by mature commercial EDA tools. An optimization algorithm of dual-port memory mapping is proposed for area, delay and power consumption, and a specific configuration scheme is given. Experiments show that when facing simple storage requirements, the mapping results are consistent with those of commercial tools; when facing complex storage requirements, the mapping results of area optimization and power optimization are improved by at least 50% compared with commercial tools Vivado.
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Key words:
- FPGA /
- Dual-port memory mapping /
- Delay optimization /
- Area optimization /
- Power optimization
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表 1 Virtex-4存储器块配置方式
i 索引 1 2 3 4 5 6 7 地址深度 d[i] 256 512 1k 2k 4k 8k 16k 地址位宽 b[i] 8 9 10 11 12 13 14 数据位宽 w[i] 72 36 18 9 4 2 1 
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表 2 AlgoPower映射策略方案
序号 视图 配置 地址端口连接 数据端口连接 译码/选通 #1 V1 1k×18 a9 a8 ··· a1 a0 d33 d32 ··· d17 d16 – V2 1k×18 a10 a9 ··· a2 a1 d25 d24 ··· d9 d8 (a0) = 0 V3 V4 1k×18 a11 a10 ··· a3 a2 d21 d20 ··· d5 d4 (a1 a0) = 00 #2 V1 1k×18 a9 a8 ··· a1 a0 d51 d50 ··· d35 d34 – V2 1k×18 a10 a9 ··· a2 a1 d43 d42 ··· d27 d26 (a0) = 0 V3 V4 1k×18 a11 a10 ··· a3 a2 d21 d20 ··· d5 d4 (a1 a0) = 01 #3 V1 1k×18 a9 a8 ··· a1 a0 d69 d68 ··· d53 d52 – V2 1k×18 a10 a9 ··· a2 a1 d25 d24 ··· d9 d8 (a0) = 1 V3 V4 1k×18 a11 a10 ··· a3 a2 d21 d20 ··· d5 d4 (a1 a0) = 10 #4 V1 1k×18 a9 a8 ··· a1 a0 d87 d86 ··· d71 d70 – V2 1k×18 a10 a9 ··· a2 a1 d43 d42 ··· d27 d26 (a0) = 1 V3 V4 1k×18 a11 a10 ··· a3 a2 d21 d20 ··· d5 d4 (a1 a0) = 11 #5 V1 1k×18 a9 a8 ··· a1 a0 d15 d14 ··· d1 d0 – V2 2k×9 a10 a9 ··· a1 a0 d7 d6 ··· d1 d0 – V3 V4 4k×4 a11 a10 ··· a1 a0 d3 d2 d1 d0 –
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表 3 AlgoDelay映射策略方案
序号 视图 配置 地址端口连接 数据端口连接 译码/选通 #1 V1 8k×2 a12 a11 ··· a1 a0 d1 d0 (a′15 a′14) = 00 V2 4k×4 a11 a10 ··· a1 a0 d3 d2 d1 d0 (a′14 a′13) = 00 V3 V4 2k×8 a10 a9 ··· a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 (a′13 a′12) = 00 #2 V1 8k×2 a12 a11 ··· a1 a0 d1 d0 (a′15 a′14) = 11 V2 4k×4 a11 a10 ··· a1 a0 d3 d2 d1 d0 (a′14 a′13) = 11 V3 V4 2k×8 a10 a9 ··· a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 (a′13 a′12) = 11 #3 V1 16k×1 a12 a11 ··· a1 a0 d1 (a′15 a′14) = 01 V2 8k×2 a11 a10 ··· a1 a0 d3 d1 (a′14 a′13) = 01 V3 V4 4k×4 a10 a9 ··· a1 a0 d7 d5 d3 d1 (a′13 a′12) = 01 #4 V1 16k×1 a12 a11 ··· a1 a0 d0 (a′15 a′14) = 01 V2 8k×2 a11 a10 ··· a1 a0 d2 d0 (a′14 a′13) = 01 V3 V4 4k×4 a10 a9 ··· a1 a0 d6 d4 d2 d0 (a′13 a′12) = 01 #5 V1 4k×4 a13 a12 ··· a1 a0 d3 d2 d1 d0 (a′15 a′14) = 10 V2 2k×8 a12 a11 ··· a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 (a′14 a′13) = 10 V3 V4 1k×16 a11 a10 ··· a1 a0 d15 d14 ··· d1 d0 (a′13 a′12) = 10
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表 4 功耗优化实验结果
序号 地址1 读1 写1 地址2 读2 写2 Vivado平均触发数 AlgoPower平均触发数 优化比例(%) 1 10 32 32 10 32 32 1 1.00 0 2 10 32 64 10 32 256 8 1.14 85.7 3 11 16 32 10 32 256 8 1.09 86.4 4 11 16 32 10 32 128 4 1.06 73.5 5 11 16 256 10 32 128 8 1.33 83.4 6 11 32 32 10 64 64 2 1.00 50.0 7 11 32 64 10 64 128 4 1.11 72.2 8 11 16 32 11 16 128 4 1.05 73.8
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表 5 延时优化实验结果
序号 V1(rd) V2(rd) V3(wr) V4(wr) AlgoDelay选通级数 1 36k×4 72k×2 18k×8 9k×16 V1: 2 V2: 3 2 81k×16 324k×4 162k×8 162k×8 V1: 3 V2: 5 3 18k×4 9k×8 36k×2 18k×4 V1: 2 V2: 1 4 4k×25 2k×50 1k×100 4k×25 V1: 1 V2: 1 5 16k×4 32k×2 8k×8 4k×16 V1: 1 V2: 2
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表 6 面积优化实验结果
序号 地址1 读1 写1 地址2 读2 写2 Vivado使用资源 AlgoArea使用资源 优化比例(%) 1 10 32 32 10 32 32 2 2 0 2 10 32 64 10 32 256 8 4 50 3 11 16 32 10 32 256 8 4 50 4 11 16 32 10 32 128 4 2 50 5 11 16 256 10 32 128 4 4 0 6 11 32 32 10 64 64 4 4 0 7 11 32 64 10 64 128 4 4 0 8 11 16 32 11 16 128 4 2 50
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