基于FPGA的卷积神经网络硬件加速器设计

秦华标; 曹钦平

doi:10.11999/JEIT190058

基于FPGA的卷积神经网络硬件加速器设计

doi: 10.11999/JEIT190058

秦华标^,,
曹钦平

华南理工大学电子与信息学院广州 510641

基金项目: 广东省科技计划项目(2014B090910002)

详细信息

作者简介:
秦华标：男，1967年生，教授，研究方向为智能信息处理、无线通信网络、嵌入式系统、FPGA设计

曹钦平：男，1995年生，硕士生，研究方向为集成电路设计

通讯作者:
秦华标　eehbqin@scut.edu.cn

中图分类号: TP331
计量
- 文章访问数: 4452
- HTML全文浏览量: 1975
- PDF下载量: 312
- 被引次数: 0
出版历程
- 收稿日期: 2019-01-22
- 修回日期: 2019-06-10
- 网络出版日期: 2019-06-20
- 刊出日期: 2019-11-01

Design of Convolutional Neural Networks Hardware Acceleration Based on FPGA

Huabiao QIN^,,
Qinping CAO

School of Electronics and Information Engineering, South China University of Technology, Guangzhou 510641, China

Funds: The Science and Technology Project of Guangdong Provience (2014B090910002)

摘要

摘要: 针对卷积神经网络(CNN)计算量大、计算时间长的问题，该文提出一种基于现场可编程逻辑门阵列(FPGA)的卷积神经网络硬件加速器。首先通过深入分析卷积层的前向运算原理和探索卷积层运算的并行性，设计了一种输入通道并行、输出通道并行以及卷积窗口深度流水的硬件架构。然后在上述架构中设计了全并行乘法-加法树模块来加速卷积运算和高效的窗口缓存模块来实现卷积窗口的流水线操作。最后实验结果表明，该文提出的加速器能效比达到32.73 GOPS/W，比现有的解决方案高了34%，同时性能达到了317.86 GOPS。
- 卷积神经网络 /
- 硬件加速 /
- 现场可编程逻辑门阵列 /
- 计算并行 /
- 深度流水
Abstract: Considering the large computational complexity and the long-time calculation of Convolutional Neural Networks (CNN), an Field-Programmable Gate Array(FPGA)-based CNN hardware accelerator is proposed. Firstly, by deeply analyzing the forward computing principle and exploring the parallelism of convolutional layer, a hardware architecture in which parallel for the input channel and output channel, deep pipeline for the convolution window is presented. Then, a full parallel multi-addition tree is designed to accelerate convolution and efficient window buffer to implement deep pipelining operation of convolution window. The experimental results show that the energy efficiency ratio of proposed accelerator reaches 32.73 GOPS/W, which is 34% higher than the existing solutions, as the performance reaches 317.86 GOPS.
- Convolutional Neural Networks (CNN) /
- Hardware acceleration /
- FPGA /
- Parallel computation /
- Deep pipeline

HTML全文

图 1 卷积层运算过程

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图 2 1个输入通道的卷积运算过程

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图 3 N个输入通道的卷积窗口并行计算

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图 4 累加器并行运算

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图 5 经典加法树

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图 6 本文设计的加法树

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图 7 乘法-加法树模块

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图 8 卷积窗口数据重用

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图 9 窗口缓存结构

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图 10 窗口缓存时序

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图 11 输出通道并行模块

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图 12 并行加速方案结构

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图 13 卷积窗口流水线

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图 14 FPGA, CPU, GPU的性能对比

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表 1 卷积神经网络结构参数

层名称	层结构	参数量（个）
卷积层1	卷积核大小3×3，卷积核个数15，步长1	150
激活层1	无	0
池化层1	池化大小2×2，步长2	0
卷积层2	卷积核大小6×6，卷积核个数20，步长1	10820
激活层2	无	0
池化层2	池化大小2×2，步长2	0
全连接层	输出神经元个数10	3210

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表 2 FPGA资源消耗情况

	资源	比例(%)
ALMs	89423/113560	79
Block Memory	730151/12492800	6
DSPs	342/342	100

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表 3 与文献FPGA硬件加速对比

	文献[7]	文献[11]	文献[12]	本文方法
FPGA	Zynq XC7Z045	ZynqXC7Z045	Virtex-7 VX690T	Cyclone V 5CGXF
频率(MHz)	150	100	150	100
DSP资源	780(86.7%)	824(91.6%)	1376(38%)	342(100%)
量化策略	16 bit fixed	16 bit fixed	16 bit fixed	16 bit fixed
功耗(W)	9.630	9.400	25.000	9.711
性能(GOPS)	136.97	229.50	570.00	317.86
能效比(GOPS/W)	14.22	24.42	22.80	32.73

下载: 导出CSV

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