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基于FPGA的卷积神经网络硬件加速器设计

秦华标 曹钦平

秦华标, 曹钦平. 基于FPGA的卷积神经网络硬件加速器设计[J]. 电子与信息学报, 2019, 41(11): 2599-2605. doi: 10.11999/JEIT190058
引用本文: 秦华标, 曹钦平. 基于FPGA的卷积神经网络硬件加速器设计[J]. 电子与信息学报, 2019, 41(11): 2599-2605. doi: 10.11999/JEIT190058
Huabiao QIN, Qinping CAO. Design of Convolutional Neural Networks Hardware Acceleration Based on FPGA[J]. Journal of Electronics & Information Technology, 2019, 41(11): 2599-2605. doi: 10.11999/JEIT190058
Citation: Huabiao QIN, Qinping CAO. Design of Convolutional Neural Networks Hardware Acceleration Based on FPGA[J]. Journal of Electronics & Information Technology, 2019, 41(11): 2599-2605. doi: 10.11999/JEIT190058

基于FPGA的卷积神经网络硬件加速器设计

doi: 10.11999/JEIT190058
基金项目: 广东省科技计划项目(2014B090910002)
详细信息
    作者简介:

    秦华标:男,1967年生,教授,研究方向为智能信息处理、无线通信网络、嵌入式系统、FPGA设计

    曹钦平:男,1995年生,硕士生,研究方向为集成电路设计

    通讯作者:

    秦华标 eehbqin@scut.edu.cn

  • 中图分类号: TP331

Design of Convolutional Neural Networks Hardware Acceleration Based on FPGA

Funds: The Science and Technology Project of Guangdong Provience (2014B090910002)
  • 摘要: 针对卷积神经网络(CNN)计算量大、计算时间长的问题,该文提出一种基于现场可编程逻辑门阵列(FPGA)的卷积神经网络硬件加速器。首先通过深入分析卷积层的前向运算原理和探索卷积层运算的并行性,设计了一种输入通道并行、输出通道并行以及卷积窗口深度流水的硬件架构。然后在上述架构中设计了全并行乘法-加法树模块来加速卷积运算和高效的窗口缓存模块来实现卷积窗口的流水线操作。最后实验结果表明,该文提出的加速器能效比达到32.73 GOPS/W,比现有的解决方案高了34%,同时性能达到了317.86 GOPS。
  • 图  1  卷积层运算过程

    图  2  1个输入通道的卷积运算过程

    图  3  N个输入通道的卷积窗口并行计算

    图  4  累加器并行运算

    图  5  经典加法树

    图  6  本文设计的加法树

    图  7  乘法-加法树模块

    图  8  卷积窗口数据重用

    图  9  窗口缓存结构

    图  10  窗口缓存时序

    图  11  输出通道并行模块

    图  12  并行加速方案结构

    图  13  卷积窗口流水线

    图  14  FPGA, CPU, GPU的性能对比

    表  1  卷积神经网络结构参数

    层名称层结构参数量(个)
    卷积层1卷积核大小3×3,卷积核个数15,步长1150
    激活层10
    池化层1池化大小2×2,步长20
    卷积层2卷积核大小6×6,卷积核个数20,步长110820
    激活层20
    池化层2池化大小2×2,步长20
    全连接层输出神经元个数103210
    下载: 导出CSV

    表  2  FPGA资源消耗情况

    资源比例(%)
    ALMs89423/11356079
    Block Memory730151/124928006
    DSPs342/342100
    下载: 导出CSV

    表  3  与文献FPGA硬件加速对比

    文献[7]文献[11]文献[12]本文方法
    FPGAZynq XC7Z045ZynqXC7Z045Virtex-7 VX690TCyclone V 5CGXF
    频率(MHz)150100150100
    DSP资源780(86.7%)824(91.6%)1376(38%)342(100%)
    量化策略16 bit fixed16 bit fixed16 bit fixed16 bit fixed
    功耗(W)9.6309.40025.0009.711
    性能(GOPS)136.97229.50570.00317.86
    能效比(GOPS/W)14.2224.4222.8032.73
    下载: 导出CSV
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出版历程
  • 收稿日期:  2019-01-22
  • 修回日期:  2019-06-10
  • 网络出版日期:  2019-06-20
  • 刊出日期:  2019-11-01

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