Design of Convolutional Neural Networks Accelerator Based on Fast Filter Algorithm
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摘要: 为减少卷积神经网络(CNN)的计算量，该文将2维快速滤波算法引入到卷积神经网络，并提出一种在FPGA上实现CNN逐层加速的硬件架构。首先，采用循环变换方法设计行缓存循环控制单元，用于有效地管理不同卷积窗口以及不同层之间的输入特征图数据，并通过标志信号启动卷积计算加速单元来实现逐层加速；其次，设计了基于4并行快速滤波算法的卷积计算加速单元，该单元采用若干小滤波器组成的复杂度较低的并行滤波结构来实现。利用手写数字集MNIST对所设计的CNN加速器电路进行测试，结果表明：在xilinx kintex7平台上，输入时钟为100 MHz时，电路的计算性能达到了20.49 GOPS，识别率为98.68%。可见通过减少CNN的计算量，能够提高电路的计算性能。Abstract: In order to reduce the computational complexity of Convolutional Neural Network(CNN), the two-dimensional fast filtering algorithm is introduced into the CNN, and a hardware architecture for implementing CNN layer-by-layer acceleration on FPGA is proposed. Firstly, the line buffer loop control unit is designed by using the cyclic transformation method to manage effectively different convolution windows and the input feature map data between different layers, and starts the convolution calculation acceleration unit by the flag signal to realize layer-by-layer acceleration. Secondly, a convolution calculation accelerating unit based on 4 parallel fast filtering algorithm is designed. The unit is realized by a less complex parallel filtering structure composed of several small filters. Using the handwritten digit set MNIST to test the designed CNN accelerator circuit, the results show that on the xilinx kintex7 platform, when the input clock is 100 MHz, the computational performance of the circuit reaches 20.49 GOPS, and the recognition rate is 98.68%. It can be seen that the computational performance of the circuit can be improved by reducing the amount of calculation of the CNN.
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Key words:
- Convolution Neural Network(CNN) /
- Fast filter algorithms /
- FPGA /
- Parallel structure
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表 1 MATLAB实现与FPGA实现的比较
类型 时间(ms/frams) 精度(bad/10000 frames) 数据类型 .m文件 0.7854 1.19% 双精度 .v 文件 0.01986 1.32% 16 bit定点数 
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