基于正交混淆的多硬件IP核安全防护设计

张跃军; 王佳伟; 潘钊; 张晓伟; 汪鹏君

doi:10.11999/JEIT180898

基于正交混淆的多硬件IP核安全防护设计

doi: 10.11999/JEIT180898

宁波大学信息科学与工程学院宁波 315211

基金项目: 国家自然科学基金(61871244, 61874078, 61704094)，浙江省自然科学基金(LY18F040002)，浙江省科技厅公益技术应用研究(2016C31078)，亿像素视频加密与IP加密算法与硬件开发横向项目(HK2017000135)，浙江省大学生新苗人才计划(2018R405071)，宁波大学王宽诚幸福基金

详细信息

作者简介:
张跃军：男，1982年生，副教授，研究方向为信息安全芯片理论和设计

王佳伟：男，1994年生，硕士生，研究方向为硬件安全和混淆设计

潘钊：男，1993年生，硕士生，研究方向为混淆状态机的设计与实现

张晓伟：男，1987年生，讲师，研究方向为稀土掺杂硅基薄膜发光材料与光电子器件研究

汪鹏君：男，1966年生，教授，研究方向为低功耗、高信息密度集成电路理论和设计、安全芯片理论和设计、多媒体技术及相关理论

通讯作者:
汪鹏君　wangpengjun@nbu.edu.cn

中图分类号: TP331
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出版历程
- 收稿日期: 2018-09-18
- 修回日期: 2019-03-14
- 网络出版日期: 2019-04-13
- 刊出日期: 2019-08-01

Hardware Security for Multi IPs Protection Based on Orthogonal Obfuscation

Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo 315211, China

Funds: The National Natural Science Foundation of China (61871244, 61874078, 61704094),The Natural Science Foundation of Zhejiang Provincial (LY18F040002), The S&T Plan of Zhejiang Provincial Science and Technology Department (2016C31078), Algorithms and Hardware Development of Billion Pixels Video Encryption and IP Encryption (HK2017000135), Fresh Student Talents Program of Zhejiang Province (2018R405071), The K.C. Wong Magna Fund in Ningbo University

摘要

摘要: 为了解决集成电路设计中多方合作的成员信息泄漏问题，该文提出一种基于正交混淆的多硬件IP核安全防护方案。该方案首先利用正交混淆矩阵产生正交密钥数据，结合硬件特征的物理不可克隆函数(PUF)电路，产生多硬件IP核的混淆密钥；然后，在正交混淆状态机的基础上，实现多硬件IP核的正交混淆安全防护算法；最后，利用ISCAS-85基准电路和密码算法，验证正交混淆方法的有效性。在台湾积体电路制造股份有限公司(TSMC) 65 nm工艺下测试正交混淆的多硬件IP核方案，正确密钥和错误密钥下的Toggle翻转率小于5%，在较大规模的测试电路中面积和功耗开销占比小于2%。实验结果表明，采用正交混淆的方式能够提高多硬件IP核的安全性，可以有效防御成员信息泄漏、状态翻转率分析等攻击。
- 正交混淆 /
- 合伙人组织 /
- 物理不可克隆函数 /
- 硬件IP安全性
Abstract: In order to solve the problem of member information leakage in multi-party cooperative design of integrated circuits, a orthogonal obfuscation scheme of multi-hardware IPs core security protection is proposed. Firstly, the orthogonal obfuscation matrix generates orthogonal key data, and the obfuscated key of the hardware IP core is designed with the physical feature of the Physical Unclonable Function (PUF) circuit. Then the security of multiple hardware IP cores is realized by the orthogonal obfuscation state machine. Finally, the validity of orthogonal aliasing is verified using the ISCAS-85 circuit and cryptographic algorithm. The multi-hardware IP core orthogonal obfuscation scheme is tested under Taiwan Semiconductor Manufacturing Company (TSMC) 65 nm process, the difference of Toggle flip rate between the correct key and the wrong key is less than 5%, and the area and power consumption of the larger test circuit are less than 2%. The experimental results show that orthogonal obfuscation can improve the security of multi-hardware IP cores, and can effectively defend against member information leakage and state flip rate analysis attacks.
- Orthogonal obfuscation /
- PartnerShip Organization(PSO) /
- Physical Unclonable Function(PUF) /
- Hardware IPs security

HTML全文

图 1 正交混淆方法结构框图

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图 2 IC设计团队、芯片公司以及用户的正交混淆交互协议

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图 3 正交混淆的电路实现

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图 4 正交混淆功能仿真图

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图 5 正交混淆的面积开销

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图 6 正交混淆的功耗开销

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图 7 不同加密方法在成员泄密时的安全性曲线

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图 8 Toggle仿真结果

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表 1 正交混淆算法伪代码

正交混淆算法
输入：K_user
输出：{p₁,p₂,···,p_n}
(1) 初始化正交模块
(2) 重置功能IP核
(3) 对各功能IP核分配权重
(4) for i←0 to N-1
for j←i+1 to N-1 {
do vector_j←vector_j-(vector_j[i]/vector_i[i])× 　　　　　vector_i
}
(5) for i←0 to N-1
for j←i+1 to N-1 {
do vector_i←vector_i-(vector_i[N-i]/vector_j[N-i])× 　　　　vector_j
}
(6) 矩阵O←{vector_1,vector_2,···,vector_N}^T
(7) 向量p←O×K_user

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表 2 基准电路中硬件开销情况

	基准电路面积(μm²)	测试模块面积(μm²)	混淆面积开销(μm²)	面积开销占比(%)	基准电路功耗(mW)	测试模块功耗(mW)	混淆功耗开销(mW)	功耗开销占比(%)	混淆模块延时(ns)
A1	6457.68	7391.68	934.00	12.60	0.3129	0.4392	0.1263	28.80	1.12
A1+A2	16851.96	17866.12	1014.16	5.70	3.3928	3.5517	0.1589	4.50	1.12
A1+A2+A3	32561.64	33618.80	1057.16	3.10	7.5221	7.7017	0.1796	2.30	1.15
A1+A2+A3+A4	49888.08	51038.76	1150.68	2.30	11.5796	11.7626	0.1830	1.60	1.20
注：表中A1, A2, A3和A4分别表示密码算法TDEA, SEED_3clk, MISTY1_3clk和AES中的EncCore部分。

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表 3 本文设计与文献[8–12]对比情况

文献	混淆方法	工艺(mm)	基准电路	面积(μm²)	功耗(mW)	速度(GHz)	混淆IP核数量	MILA
文献[8]	状态映射混淆	65	AES-ENC	25983.00	0.7558	–	单个	是
文献[9]	DUP	65	SEED_3clk	17506.08	3.2171	1.38	单个	是
文献[10]	ISO	65	SEED_3clk	17450.64	3.2830	1.72	单个	是
文献[11]	HARPOON	65	S38584	22995.40	6.3883	1.14	单个	是
文献[12]	Dynamic State-Deflection	65	S38584	21835.00	6.9262	0.86	单个	是
本文	正交混淆	65	SEED_3clk	17114.60	3.2815	0.98	多个	否
			AES-ENC	17326.44	4.0575	0.95		否
			s38584	20159.00	6.7456	0.83		否

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