A 10 bit Fully Differential Dual Slope Analog-to-digital Converter for Time Delay Integration CMOS Image Sensors
-
摘要: 为了满足时间延时积分(TDI)CMOS图像传感器转换全差分信号的需要，同时符合列并行电路列宽的限制，该文提出并实现了一种10 bit全差分双斜坡模数转换器(ADC)。在列并行单斜坡ADC的基础上，采用2个电容的上极板对差分输入进行采样，电容下极板接2个斜坡输出完成量化。基于电流舵结构的斜坡发生器同时产生上升和下降斜坡，2个斜坡的台阶电压大小相等。该电路使用SMIC 0.18 μm CMOS工艺设计实现，ADC以19.49 kS/s的采样频率对1.32 kHz的输入进行采样，仿真得到无杂散动态范围和有效位数分别为87.92 dB和9.84 bit。测试显示该ADC的微分非线性误差和积分非线性误差分别为–0.7/+0.6 LSB和–2.6/+2.1 LSB。Abstract: A 10 bit fully differential dual slope Analog-to-Digital Converter (ADC) for Time Delay Integration (TDI) CMOS image sensors is realized based on column-parallel single-slope ADC. Top plates of the two capacitors are used for sampling differential inputs, and the bottom plates are connected to ramp generator for conversion. Current steering is used to generate the rising and falling ramp with the same step voltage simultaneously. The proposed ADC is fabricated in SMIC 0.18 μm CMOS process. Simulated spurious free dynamic range and effective number of bits are 87.92 dB and 9.84 bit with the input frequency of 1.32 kHz at 19.49 kS/s sampling rate, respectively. Measured results show that the ADC has a differential nonlinearity of –0.7/+0.6 LSB and integral nonlinearity of –2.6/+2.1 LSB.
-
GHALLAB Y H and ISMAIL Y. CMOS based lab-on-a-chip: applications, challenges and future trends[J]. IEEE Circuits and Systems Magazine, 2014, 14(2): 27–47. doi: 10.1109/MCAS.2014.2314264 FANG Yuan, YU Ningmei, JIANG Yuquan, et al. High-precision lens-less flow cytometer on a chip[J]. Micromachines, 2018, 9(5): 227. doi: 10.3390/mi9050227 HUANG Xiwei, JIANG Yu, LIU Xu, et al. Machine learning based single-frame super-resolution processing for lensless blood cell counting[J]. Sensors, 2016, 16(11): E1836. doi: 10.3390/s16111836 LIU Xu, HUANG Xiwei, JIANG Yu, et al. A microfluidic cytometer for complete blood count with a 3.2-Megapixel, 1.1-μm-Pitch super-resolution image sensor in 65-nm BSI CMOS[J]. IEEE Transactions on Biomedical Circuits and Systems, 2017, 11(4): 794–803. doi: 10.1109/TBCAS.2017.2697451 YIN C, LIAO Ting, LIU Kuanlin, et al. A 32-stage 15-b digital time-delay integration linear CMOS image sensor with data prediction switching technique[J]. IEEE Transactions on Electron Devices, 2017, 64(3): 1167–1173. doi: 10.1109/TED.2017.2655143 KIM D and SONG M. An enhanced dynamic-range CMOS image sensor using a digital logarithmic single-slope ADC[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2012, 59(10): 653–657. doi: 10.1109/TCSII.2012.2213359 JEON B K, HONG S K, and KWON O K. A low-power 10-bit single-slope ADC using power gating and multi-clocks for CMOS image sensors[C]. Proceedings of 2016 International SoC Design Conference, Jeju, South Korea, 2016: 257–258. SNOEIJ M F, THEUWISSEN A J P, MAKINWA K A A, et al. Multiple-ramp column-parallel ADC architectures for CMOS image sensors[J]. IEEE Journal of Solid-State Circuits, 2007, 42(12): 2968–2977. doi: 10.1109/JSSC.2007.908720 PARK H, LEE J, KIM J, et al. High frame rate VGA CMOS image sensor using two-step single slope ADCs[C]. Proceedings of 2016 IEEE Asia Pacific Conference on Circuits and Systems, Jeju, South Korea, 2016: 571–572. LYU Nan, YU Ningmei, and ZHANG Hejiu. A high-speed column-parallel time-digital single-slope ADC for CMOS image sensors[J]. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2016, E99-A(2): 555–559. doi: 10.1587/transfun.E99.A.555 KIM D, SONG M, CHOE B, et al. A multi-resolution mode CMOS image sensor with a novel two-step single-slope ADC for intelligent surveillance systems[J]. Sensors, 2017, 17(7): E1497. doi: 10.3390/s17071497 XIA Yu, NIE Kaiming, XU Jiangtao, et al. A two-step analog accumulator for CMOS TDI image sensor with temporal undersampling exposure method[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(3): 1104–1117. doi: 10.1109/TVLSI.2015.2439262 SHIRAI E. CMOS multistage preamplifier design for high-speed and high-resolution comparators[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2007, 54(2): 166–170. doi: 10.1109/TCSII.2006.883091 ZHU Y, CHAN C H, CHIO U F, et al. A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2010, 45(6): 1111–1121. doi: 10.1109/JSSC.2010.2048498 TANG Kai, MENG Qiao, WANG Zhigong, et al. A low power 20 GHz comparator in 90 nm COMS technology[J]. Journal of Semiconductors, 2014, 35(5): 055002. doi: 10.1088/1674-4926/35/5/055002 RAZAVI B. The current-steering DAC[J]. IEEE Solid-State Circuits Magazine, 2018, 10(1): 11–15. doi: 10.1109/MSSC.2017.2771102 MAO Wei, LI Yongfu, HENG C H, et al. High dynamic performance current-steering DAC design with nested-segment structure[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018, 26(5): 995–999. doi: 10.1109/TVLSI.2018.2791462 -
下载:
图(8) / 表(1)
计量
- 文章访问数: 2791
- HTML全文浏览量: 1289
- PDF下载量: 91
- 被引次数: 0
下载:
