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一种面向粗粒度可重构阵列的硬件木马检测算法的设计与实现

严迎建 刘敏 邱钊洋

严迎建, 刘敏, 邱钊洋. 一种面向粗粒度可重构阵列的硬件木马检测算法的设计与实现[J]. 电子与信息学报, 2019, 41(5): 1257-1264. doi: 10.11999/JEIT180484
引用本文: 严迎建, 刘敏, 邱钊洋. 一种面向粗粒度可重构阵列的硬件木马检测算法的设计与实现[J]. 电子与信息学报, 2019, 41(5): 1257-1264. doi: 10.11999/JEIT180484
Yingjian YAN, Min LIU, Zhaoyang QIU. Design and Implementation of Hardware Trojan Detection Algorithm for Coarse-grained Reconfigurable Arrays[J]. Journal of Electronics & Information Technology, 2019, 41(5): 1257-1264. doi: 10.11999/JEIT180484
Citation: Yingjian YAN, Min LIU, Zhaoyang QIU. Design and Implementation of Hardware Trojan Detection Algorithm for Coarse-grained Reconfigurable Arrays[J]. Journal of Electronics & Information Technology, 2019, 41(5): 1257-1264. doi: 10.11999/JEIT180484

一种面向粗粒度可重构阵列的硬件木马检测算法的设计与实现

doi: 10.11999/JEIT180484
详细信息
    作者简介:

    严迎建:男,1973 年生,教授,研究方向为安全专用芯片设计技术

    刘敏:女,1995年生,硕士生,研究方向为安全专用芯片设计技术硬件木马检测

    邱钊洋:男,1991年生,博士生,研究方向为信号分析与软件无线电

    通讯作者:

    刘敏 15515671017@163.com

  • 中图分类号: TN406

Design and Implementation of Hardware Trojan Detection Algorithm for Coarse-grained Reconfigurable Arrays

  • 摘要: 硬件木马检测已成为当前芯片安全领域的研究热点,现有检测算法大多面向ASIC电路和FPGA电路,且依赖于未感染硬件木马的黄金芯片,难以适应于由大规模可重构单元组成的粗粒度可重构阵列电路。因此,该文针对粗粒度可重构密码阵列的结构特点,提出基于分区和多变体逻辑指纹的硬件木马检测算法。该算法将电路划分为多个区域,采用逻辑指纹特征作为区域的标识符,通过在时空两个维度上比较分区的多变体逻辑指纹,实现了无黄金芯片的硬件木马检测和诊断。实验结果表明,所提检测算法对硬件木马检测有较高的检测成功率和较低的误判率。
  • 图  1  粗粒度可重构密码阵列硬件结构

    图  2  不同触发信号的硬件木马示意

    图  3  CGRCA电路分区示意

    图  4  逻辑指纹检测原理

    图  5  子任务不同变体执行实例

    图  6  不同区域对比示意

    图  7  算法检测流程示意图

    图  8  硬件木马设计示意图

    图  9  不同检测算法结果对比

    表  1  检测结果可能情况

    实际情况检测情况
    不含硬件木马含有硬件木马
    不含硬件木马正确错误
    含有硬件木马错误正确
    下载: 导出CSV

    表  2  待测电路具体情况

    电路编号分区数线网数输入输出木马面积占比(%)
    原始电路162604944/
    C-101626049440.015
    S-101626049440.025
    CS-5/51626049440.031
    下载: 导出CSV

    表  3  检测算法实验结果对比(%)

    电路编号ATMR DRMaSV RLF 本文算法
    RsRfAPCORsRfAPCORsRfAPCORsRfAPCO
    C-10AES91.11.0291.3 97.20.3793.7 93.10.4552.1 97.30.3193.2
    SMS492.90.9891.797.30.3593.893.20.4154.197.70.2993.7
    A5/189.70.9989.993.50.3293.991.10.3752.794.70.3092.1
    均值91.21.0091.096.00.3593.892.50.4153.096.60.3093.0
    S-10AES89.71.1390.293.20.3993.589.60.4753.793.40.3293.3
    SMS488.51.0590.393.40.3893.990.10.4453.993.30.3192.9
    A5/185.31.0189.790.50.3393.490.20.3954.192.70.3391.7
    均值87.81.0690.192.40.3793.690.00.4353.993.10.3292.6
    CS-5/5AES90.11.0091.095.30.3993.893.00.4654.695.40.2792.1
    SMS491.30.9991.395.60.3794.092.70.4354.795.60.2793.2
    A5/189.31.0190.793.70.3593.592.30.3953.393.70.3192.7
    均值90.21.0091.094.90.3793.892.70.4354.294.90.2892.7
    均值89.81.0290.794.40.3693.791.70.4253.794.90.3092.8
    下载: 导出CSV
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    KITSOS P, SIMOS D E, TORRES-Jimenez J, et al. Exciting FPGA cryptographic trojans using combinatorial testing[C]. IEEE International Symposium on Software Reliability Engineering, Gaithersbury, USA, 2016: 69–76.
    赵剑锋, 史岗. 硬件木马研究动态综述[J]. 信息安全学报, 2017, 2(1): 74–90. doi: 10.19363/j.cnki.cn10-1380/tn.2017.01.006

    ZHAO Jianfeng and SHI Gang. A survey on the studies of hardware trojan[J]. Journal of Cyber Security, 2017, 2(1): 74–90. doi: 10.19363/j.cnki.cn10-1380/tn.2017.01.006
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    KHALEGHI B, AHARI A, ASADI H, et al. FPGA-based protection scheme against hardware trojan horse insertion using dummy logic[J]. IEEE Embedded Systems Letters, 2015, 7(2): 46–50. doi: 10.1109/LES.2015.2406791
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出版历程
  • 收稿日期:  2018-05-21
  • 修回日期:  2018-09-20
  • 网络出版日期:  2018-10-22
  • 刊出日期:  2019-05-01

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