Sample and Hold Front-end Circuit for 14-bit 210 MS/s Charge-domain ADC
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摘要:
该文提出一种用于电荷域流水线模数转换器(ADC)的高精度输入共模电平不敏感采样保持前端电路。该采样保持电路可对电荷域流水线ADC中由输入共模电平误差引起的共模电荷误差进行补偿。所提出的高精度输入共模电平不敏感采样保持电路被运用于一款14位210 MS/s电荷域ADC中，并在1P6M 0.18 μm CMOS工艺下实现。测试结果显示，该14位ADC电路在210 MS/s条件下对于30.1 MHz单音正弦输入信号得到的无杂散动态范围为85.4 dBc，信噪比为71.5 dBFS，而ADC内核功耗仅为205 mW，面积为3.2 mm2。
Abstract:A high precision common mode level insensitive sample and hold front-end circuit for charge domain pipelined Analog-to-Digital Converter (ADC) is proposed. The sample and hold circuit can be used to compensate the common mode charge errors caused by the variation of input common mode level in charge domain pipelined ADCs. Based on the proposed sample and hold circuit, a 14-bit 210 MS/s charge domain pipelined ADC is designed and realized in a 1P6M 0.18 μm CMOS process. Test results show the 14-bit 210 MS/s ADC achieves the signal-to-noise ratio of 71.5 dBFS and the spurious free dynamic range of 85.4 dBc, with 30.1 MHz input single tone signal at 210 MS/s, while the ADC core consumes the power consumption of 205 mW and occupies an area of 3.2 mm2.
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表 1 ADC性能对比
技术指标 精度
(bit)采样
(MS/s)SNR
(dB)SFDR
(dB)电源电压
(V)工艺
(nm)内核功耗
(mW)内核面积
(mm2)FOM(pJ/step)
功耗/(${{2}^{{\rm{ENOB}}}} \cdot {\rm{f}}$clk)文献[4] 14 500 64.8 92.7 1.8/3.3 180 550 2.5** 0.71 文献[5] 14 1000 69.0 86.0 1.2/2.5 65 1200 5.0 0.55 文献[15] 14 200 68.5 88.5 1.8 180 460 22.5* 1.07 文献[16] 14 250 68.5 94.7 1.8 180 300 3.6 0.57 本文 14 210 71.5 85.4 1.8 180 205 3.2 0.39 注：*该ADC为时间交织结构；**该ADC采用SiGe BiCMOS工艺 
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