High Throughput Dual-mode Reconfigurable Floating-point FFT Processor
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摘要: 高吞吐浮点可灵活重构的快速傅里叶变换(FFT)处理器可满足尖端雷达实时成像和高精度科学计算等多种应用需求。与定点FFT相比，浮点运算复杂度更高，使得浮点型FFT的运算吞吐率与其实现面积、功耗之间的矛盾问题尤为突出。鉴于此，为降低运算复杂度，首先将大点数FFT分解成若干个小点数基2k 级联子级实现，提出分别针对128/256/512/1024/2048点FFT的优化混合基算法。同时，结合所提出同时支持单通道单精度和双通道半精度两种浮点模式的新型融合加减与点乘运算单元，首次提出一款高吞吐率双模浮点可变点FFT处理器结构，并在28 nm标准CMOS工艺下进行设计并实现。实验结果表明，单通道单精度和双通道半精度浮点两种模式下的运算吞吐率和输出平均信号量化噪声比分别为3.478 GSample/s, 135 dB和6.957 GSample/s, 60 dB。归一化吞吐率面积比相比于现有其他浮点FFT实现可提高约12倍。Abstract: In the advanced applications of real-time radar imaging and high-precision scientific computing systems, the design of high throughput and reconfigurable Floating-Point (FP) FFT accelerator is significant. Achieving high throughput FP FFT with low area and power cost poses a greater challenge due to high complexity of FP operations in comparison to fixed-point implementations. To address these issues, a serial of mixed-radix algorithms for 128/256/512/1024/2048-point FFT are proposed by decomposing long FFT into short implementations with cascaded radix-2k stages so that the complexity of multiplications can be significantly reduced. Besides, two novel fused FP add-subtract and dot-product units for dual-mode functionality are proposed, which can either compute on a pair of double precision operands or on two pairs of single precision operands in parallel. Thus, a high throughput dual-mode floating-point variable length FFT is designed. The proposed processor is implemented based on SMIC 28 nm CMOS technology. Simulation results show that the throughput and Signal-to-Quantization Noise Ratio (SQNR) in single-channel single precision and dual-channel half precision floating-point mode are 3.478 GSample/s, 135 dB and 6.957 GSample/s, 60 dB respectively. Compare to the other FP FFT, this processor can achieve 12 times improvement of normalized throughput-area ratio.
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表 1 本文所提出的混合基算法
点数 优化算法 每个子级相应的基底 1 2 3 4 5 6 7 8 9 10 128 23-22-22 4 8 128 4 16 4 256 24-22-22 4 16 4 256 4 16 4 512 24-22-23 4 16 4 512 4 32 4 8 1024 25-22-23 4 8 32 4 1024 4 32 4 8 2048 25-23-23 4 8 32 4 2048 4 8 64 4 8 
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表 2 双模浮点融合加减运算单元关键路径
模块名 流水级 延时(ns) 数据提取与尾数生成 1 0.43 指数比较与尾数交换 1 0.77 指数阶差与尾数对齐 2 1.98 尾数求和差 3 1.47 LZA 3 0.35 规格化左移 3 0.16
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表 3 双模浮点融合加减运算单元性能比较结果
参数 文献[6] 参考结构T1 本文 工艺 (nm) 45 28 28 归一化面积 (μm2) 5226 (100%) 2665 (51%) 2317 (44%) 工作频率 (MHz) 1920 500 435 计算延迟 (ns) 1.0 6.0 6.9 功耗 (mW) 5.2 0.6 0.4 功耗×周期 2.70 (100%) 1.20 (44%) 0.84 (31%)
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表 4 双模浮点融合点乘运算单元关键路径
模块名 流水级 延时(ns) 数据提取与指数比较 1 0.33 尾数部分积相乘 1 0.87 指数阶差与乘积对齐 2 1.25 双模4:2 CSA 2 0.20 双加法舍入路径 2 0.53 LZD与规格化左移 3 1.98
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表 5 双模浮点融合点乘运算单元性能比较结果
参数 文献[5] 参考结构T2 本文 工艺 (nm) 45 28 28 归一化面积 (μm2) 12865 (100%) 10336 (80%) 10701 (83%) 工作频率 (MHz) 1493 500 435 计算延迟 (ns) 2.1 6.0 6.9 功耗 (mW) 16.9 2.7 2.5 功耗×周期 11.3 (100%) 5.3 (47%) 5.6 (50%)
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表 6 双模浮点FFT整体性能对比
性能参数 文献[2] 文献[9] 文献[16] 本文 工艺 (nm) 90 65 55 28 FFT结构 基于存储器 Hybrid MDF MDF FFT点数 512 1024 1024 128/256/512/1024/2048 并行度 8 1 1 8 数据类型：字长 (bit) 块浮点：12 浮点：32 定点：16 浮点：32/浮点：16 平均输出SQNR (dB) 57 139 55 SP：135/HP：60 时钟频率 (MHz) 324 400 200 435 计算时间 (μs) 0.3 2.6 5.1 0.2/0.3/0.6/1.1/2.2 运算吞吐率 (MSample/s) 2592 400 200 SP：3478/HP：6957 平均功耗 (mW) 42 417 8 104 @435 MHz 有效面积 (mm2) 0.93 1.19 0.15 1.41 归一化面积 10.0 22.1 1.9 16.0 归一化吞吐率面积比 259 18 103 SP：220/HP：440
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