面向全同态加密的有限域FFT算法FPGA设计

施佺; 韩赛飞; 黄新明; 孙玲; 谢星; 唐天泽

doi:10.11999/JEIT170312

面向全同态加密的有限域FFT算法FPGA设计

doi: 10.11999/JEIT170312

1.
(南通大学电子信息学院南通 226019) ②(江苏省专用集成电路设计重点实验室南通 226019)

基金项目:

国家自然科学基金(61571246)，南通大学杏林学院自然科学基金(13010538)

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出版历程
- 收稿日期: 2017-04-10
- 修回日期: 2017-07-19
- 刊出日期: 2018-01-19

Design of Finite Field FFT for Fully Homomorphic Encryption Based on FPGA

1.
(School of Electronic Information, Nantong University, Nantong 226019, China)

Funds:

The National Natural Science Foundation of China (61571246), The Natural Science Foundation of Xinglin College of Nantong University (13010538)

摘要

摘要: 大数乘法是全同态加密算法中一个不可或缺的单元模块，也是其中耗时最多的模块，设计一个性能优良的大数乘法器有助于推进全同态加密的实用化进程。针对SSA大数乘法器的实现需求，该文采用可综合Verilog HDL语言完成了一个1624 bit有限域FFT算法的FPGA设计，通过构建树型大数求和单元和并行化处理方法有效提高了FFT算法的速度。与VIM编译环境下的系统级仿真结果比较，验证了有限域FFT算法FPGA设计的正确性。
- 全同态加密 /
- 大数乘法 /
- 有限域快速傅里叶变换 /
- 现场可编程门阵列
Abstract: Large multiplier is an indispensable module in fully homomorphic encryption, while is also the most time-consuming module. Therefore, design of a large multiplier with good performance is help to promote the practical process of fully homomorphic encryption. Aimed at the demand of SSA (Sch?nhage-Strassen Algorithm) large multiplier, a 1624 bit finite field FFT based on FPGA is designed by using Verilog HDL language. By constructing the tree type large sum unit and using parallel processing method, the speed of FFT algorithm is improved effectively. And its correctness is proved by comparing with the system level simulation results in VIM compiler environment.
- Fully homomorphic encryption /
- Large multiplier /
- Finite field FFT /
- Field Programmable Gate Array (FPGA)

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参考文献(24)

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