基于数字锁相环的星载光谱仪本地时钟源设计

田禹泽; 王煜; 代海山; 方华; 刘文清

doi:10.11999/JEIT170088

基于数字锁相环的星载光谱仪本地时钟源设计

doi: 10.11999/JEIT170088

基金项目:

国家自然科学基金(41275037)，安徽省杰出青年科学基金(1308085JGD03)

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- 被引次数: 0
出版历程
- 收稿日期: 2017-01-23
- 修回日期: 2017-05-03
- 刊出日期: 2017-10-19

Design of Local Clock Source of Satellite Borne Spectrometer Based on Digital Phase Locked Loop

Funds:

The National Natural Science Foundation of China (41275037), Anhui Province Outstanding Youth Science Foundation (1308085JGD03)

摘要

摘要: 该文针对太阳同步轨道卫星由于通讯误码导致卫星时钟不正常翻转造成的错误，提出了纠错策略。基于卫星时钟和本地时钟授时误差互补的特点，设计了一种应用于低频输入信号和大倍频系数条件下的数字锁相环(DPLL)，利用数字锁相环使本地时钟跟踪卫星时钟秒脉冲的相位波动，实时消除本地时钟的累积误差。对该时钟源进行了理论分析和实验验证，用现场可编程门阵列(FPGA)予以实现。实验表明，该设计实现的时钟源可以实时纠正卫星时钟出现的秒脉冲不正常翻转、秒脉冲丢失、时间包跳变、时间包丢失等错误，最短可以在5个输入时钟周期内进入锁定状态，稳定工作时每秒累积误差小于100 s，可作为星载光谱仪本地时钟源使用。
- 数字锁相环 /
- 反馈控制 /
- 比例积分控制 /
- 倍频 /
- FPGA
Abstract: Under the condition of working in sun-synchronous orbit, the error correction strategy is put forward due to the error caused by the communication error. According to the complementary error characteristics between satellite clock and local clock, a Digital Phase Locked Loop (DPLL) is designed, which is applied to the low frequency input signal and the large frequency multiplication factor. The local clock tracks the satellite clock pulse phase fluctuations and eliminates the accumulate error constantly. The complete design is developed with Field Programmable Gate Array (FPGA) devices and the detailed theoretical analysis and experimental results are presented. Experiments show that the design of the clock source can correct the abnormal flip or lose of second pulse and jump or lose of broadcast time package constantly. It can enter the lock state in 5 input clock cycles, and the cumulative error is less than 100 s. It can be used as the local clock source of satellite borne equipment.
- Digital Phase Locked Loop (DPLL) /
- Feedback control /
- Proportional integral control /
- Frequency- multiplier /
- FPGA

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