刘保军, 蔡理, 刘小强, 等. 纳米CMOS电路在单粒子效应下可靠性研究进展[J]. 微纳电子技术, 2016, 53(1): 1-6. doi: 10.13250/j.cnki.wndz.2016.01.001.
|
LIU Baojun, CAI Li, LIU Xiaoqiang, et al. Research advance in reliability for nano-meter CMOS circuits under single event effects[J]. Micronanoelectronic Technology, 2016, 53(1): 1-6. doi: 10.13250/j.cnki.wndz.2016.01.001.
|
UEMURA T, LEE S, PARK J, et al. Investigation of logic circuit soft error rate (SER) in 14 nm FinFET technology[C]. IEEE International Reliability Physics Symposium, Pasadena, CA, 2016: 3B-4-1-3B-4-4.
|
LI J and DRAPER J. Joint soft-error-rate (SER) estimation for combinational logic and sequential elements[C]. IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, PA, USA, 2016: 737-742.
|
HOLCOMB D, LI W, and SESHIA S A. Design as you see FIT: System-level soft error analysis of sequential circuits[C]. DATE09 the Conference on Design, Automation and Test in Europe, Leuven Belgium, 2009: 785-790.
|
靳松. CMOS集成电路老化效应的分析、预测及优化[D]. [博士论文], 中国科学院研究生院, 2011.
|
JIN Song. Analysis, forecasting and optimization technology research for aging effects of CMOS integrated circuit[D]. [Ph. D. dissertation], Graduate School of the Chinese Academy of Sciences, 2011.
|
RAMAKRISHNAN K, RAJARAMAN R, SURESH S, et al. Variation impact on SER of combinational circuits[C]. 8th International Symposium on Quality Electronic Design (ISQED), Washington, DC, USA, 2007: 911-916.
|
BAGATIN M, GERARDIN S, PACCAGNELLA A, et al. Impact of NBTI aging on the single-event upset of SRAM cells[J]. IEEE Transactions on Nuclear Science, 2010, 57(6): 3245-3250. doi: 10.1109/TNS.2010.2084100.
|
HARADA R, MITSUYAMA Y, HASHIMOTO M, et al. Impact of NBTI-induced pulse-width modulation on SET pulse-width measurement[J]. IEEE Transactions on Nuclear Science, 2013, 60(4): 2630-2634. 10.1109/TNS.2012.2232680.
|
LIN C Y H, HUANG R H-M, WEN C H-P, et al. Aging-aware statistical soft-error-rate analysis for nano-scaled CMOS designs[C]. International Symposium on VLSI design, Hstinchu, 2013: 1-4.
|
闫爱斌, 梁华国, 黄正峰, 等. 考虑NBTI效应的组合电路软差错率计算方法[J]. 计算机辅助设计与图形学学报, 2015, 27(8): 1562-1569. doi: 10.3969/j.issn.1003-9775.2015.08.026.
|
YAN Aibin, LIANG Huaguo, HUANG Zhengfeng, et al. Aging-aware soft error rate analysis for nano-scaled CMOS circuits[J]. Journal of Computer-Aided Design Computer Graphics, 2015, 27(8): 1562-1569. doi: 10.3969/j.issn.1003- 9775.2015.08.026.
|
ROSSI D, OMANA M, METRA C, et al. Impact of bias temperature instability on soft error susceptibility[J]. IEEE Transactions on VLSI Systems, 2015, 23(4): 743-751. doi: 10.1109/TVLSI.2014.2320307.
|
ALAM M A and MAHAPATRA S. A comprehensive model of PMOS NBTI degradation[J]. Microelectronics Reliability, 2005, 45(1): 71-81. doi: 10.1016/j.microrel.2004.03.019.
|
KHAN S, HAMIDIOUI S, KUKNER H, et al. BTI impact on logical gates in nano-scale CMOS technology[C]. IEEE International Symposium on Design Diagnostics of Electronic Circuits Systems, Tallinn, Estonia, 2012: 348-353.
|
PAUL B C, KANG K, KUFLUOGLU H, et al. Negative bias temperature instability: Estimation and design for improved reliability of nanoscale circuits[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007, 26(4): 743-751. doi: 10.1109/TCAD.2006.884870.
|
RABAEY J M. 数字集成电路设计透视[M]. 北京: 清华大学出版社, 1998: 133-134.
|
RABAEY J M. Digital Integrated CircuitsA Design Perspective[M]. Beijing: Tsinghua University Press, 1998: 133-134.
|
HALDUN K and MUHAMMAD A A. A generalized reaction- diffusion model with explicit H-H2 dynamics for negative- bias-temperature-instability (NBTI) degradation[J]. IEEE Transactions on Electron Devices, 2007, 54(5): 1101-1107. doi: 10.1109/TED.2007.893809.
|
KRISHNAN A T, REDDY V, CHAKRAVARTHI S, et al. NBTI impact on transistor and circuit: Models, mechanisms and scaling effects [MOSFETs][C]. IEEE International Electron Devices Meeting, Washington, DC, USA, 2003: 14.5.1-14.5.4.
|