高级搜索

留言板

尊敬的读者、作者、审稿人, 关于本刊的投稿、审稿、编辑和出版的任何问题, 您可以本页添加留言。我们将尽快给您答复。谢谢您的支持!

姓名
邮箱
手机号码
标题
留言内容
验证码

考虑偏置温度不稳定性的软差错率分析

王真 江建慧 陈乃金

王真, 江建慧, 陈乃金. 考虑偏置温度不稳定性的软差错率分析[J]. 电子与信息学报, 2017, 39(7): 1640-1645. doi: 10.11999/JEIT161113
引用本文: 王真, 江建慧, 陈乃金. 考虑偏置温度不稳定性的软差错率分析[J]. 电子与信息学报, 2017, 39(7): 1640-1645. doi: 10.11999/JEIT161113
WANG Zhen, JIANG Jianhui, CHEN Naijin. Bias Temperature Instability-aware Soft Error Rate Analysis[J]. Journal of Electronics & Information Technology, 2017, 39(7): 1640-1645. doi: 10.11999/JEIT161113
Citation: WANG Zhen, JIANG Jianhui, CHEN Naijin. Bias Temperature Instability-aware Soft Error Rate Analysis[J]. Journal of Electronics & Information Technology, 2017, 39(7): 1640-1645. doi: 10.11999/JEIT161113

考虑偏置温度不稳定性的软差错率分析

doi: 10.11999/JEIT161113
基金项目: 

国家自然科学基金(61432017, 61404092),上海电力学院人才启动基金(K-2013-017),上海高校青年教师资助计划项目(Z2015-074),上海市科委地方能力建设项目(15110500700)

Bias Temperature Instability-aware Soft Error Rate Analysis

Funds: 

The National Natural Science Foundation of China (61432017, 61404092), The Talented People Introduction Foundation of Shanghai University of Electric Power (K-2013-017), The Excellent University Young Teachers Training Program of Shanghai Municipal Education Commission (Z2015-074), The Project of Shanghai Science and Technology Committee Grant (15110500700)

  • 摘要: 纳米工艺下,老化效应与软差错共同引发的集成电路可靠性问题至关重要。该文分析偏置温度不稳定性(BTI),包括负偏置温度不稳定性(NBTI)和正偏置温度不稳定性(PBTI)对软差错率的影响,提出从关键电荷值和延迟两个因素综合考虑。首先分析BTI效应下两个因素如何变化,推导了延迟受BTI影响的变化模型,介绍关键电荷的变化机理。然后探讨将两个因素结合到软差错率(SER)评估中,推导了融入关键电荷值的SER计算模型,提出将延迟的变化导入到电气屏蔽中的方法。基于ISCAS89基准电路上的实验验证了综合两种因素考虑BTI效应评估SER的有效性和准确性。
  • 刘保军, 蔡理, 刘小强, 等. 纳米CMOS电路在单粒子效应下可靠性研究进展[J]. 微纳电子技术, 2016, 53(1): 1-6. doi: 10.13250/j.cnki.wndz.2016.01.001.
    LIU Baojun, CAI Li, LIU Xiaoqiang, et al. Research advance in reliability for nano-meter CMOS circuits under single event effects[J]. Micronanoelectronic Technology, 2016, 53(1): 1-6. doi: 10.13250/j.cnki.wndz.2016.01.001.
    UEMURA T, LEE S, PARK J, et al. Investigation of logic circuit soft error rate (SER) in 14 nm FinFET technology[C]. IEEE International Reliability Physics Symposium, Pasadena, CA, 2016: 3B-4-1-3B-4-4.
    LI J and DRAPER J. Joint soft-error-rate (SER) estimation for combinational logic and sequential elements[C]. IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, PA, USA, 2016: 737-742.
    HOLCOMB D, LI W, and SESHIA S A. Design as you see FIT: System-level soft error analysis of sequential circuits[C]. DATE09 the Conference on Design, Automation and Test in Europe, Leuven Belgium, 2009: 785-790.
    靳松. CMOS集成电路老化效应的分析、预测及优化[D]. [博士论文], 中国科学院研究生院, 2011.
    JIN Song. Analysis, forecasting and optimization technology research for aging effects of CMOS integrated circuit[D]. [Ph. D. dissertation], Graduate School of the Chinese Academy of Sciences, 2011.
    RAMAKRISHNAN K, RAJARAMAN R, SURESH S, et al. Variation impact on SER of combinational circuits[C]. 8th International Symposium on Quality Electronic Design (ISQED), Washington, DC, USA, 2007: 911-916.
    BAGATIN M, GERARDIN S, PACCAGNELLA A, et al. Impact of NBTI aging on the single-event upset of SRAM cells[J]. IEEE Transactions on Nuclear Science, 2010, 57(6): 3245-3250. doi: 10.1109/TNS.2010.2084100.
    HARADA R, MITSUYAMA Y, HASHIMOTO M, et al. Impact of NBTI-induced pulse-width modulation on SET pulse-width measurement[J]. IEEE Transactions on Nuclear Science, 2013, 60(4): 2630-2634. 10.1109/TNS.2012.2232680.
    LIN C Y H, HUANG R H-M, WEN C H-P, et al. Aging-aware statistical soft-error-rate analysis for nano-scaled CMOS designs[C]. International Symposium on VLSI design, Hstinchu, 2013: 1-4.
    闫爱斌, 梁华国, 黄正峰, 等. 考虑NBTI效应的组合电路软差错率计算方法[J]. 计算机辅助设计与图形学学报, 2015, 27(8): 1562-1569. doi: 10.3969/j.issn.1003-9775.2015.08.026.
    YAN Aibin, LIANG Huaguo, HUANG Zhengfeng, et al. Aging-aware soft error rate analysis for nano-scaled CMOS circuits[J]. Journal of Computer-Aided Design Computer Graphics, 2015, 27(8): 1562-1569. doi: 10.3969/j.issn.1003- 9775.2015.08.026.
    ROSSI D, OMANA M, METRA C, et al. Impact of bias temperature instability on soft error susceptibility[J]. IEEE Transactions on VLSI Systems, 2015, 23(4): 743-751. doi: 10.1109/TVLSI.2014.2320307.
    ALAM M A and MAHAPATRA S. A comprehensive model of PMOS NBTI degradation[J]. Microelectronics Reliability, 2005, 45(1): 71-81. doi: 10.1016/j.microrel.2004.03.019.
    KHAN S, HAMIDIOUI S, KUKNER H, et al. BTI impact on logical gates in nano-scale CMOS technology[C]. IEEE International Symposium on Design Diagnostics of Electronic Circuits Systems, Tallinn, Estonia, 2012: 348-353.
    PAUL B C, KANG K, KUFLUOGLU H, et al. Negative bias temperature instability: Estimation and design for improved reliability of nanoscale circuits[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007, 26(4): 743-751. doi: 10.1109/TCAD.2006.884870.
    RABAEY J M. 数字集成电路设计透视[M]. 北京: 清华大学出版社, 1998: 133-134.
    RABAEY J M. Digital Integrated CircuitsA Design Perspective[M]. Beijing: Tsinghua University Press, 1998: 133-134.
    HALDUN K and MUHAMMAD A A. A generalized reaction- diffusion model with explicit H-H2 dynamics for negative- bias-temperature-instability (NBTI) degradation[J]. IEEE Transactions on Electron Devices, 2007, 54(5): 1101-1107. doi: 10.1109/TED.2007.893809.
    KRISHNAN A T, REDDY V, CHAKRAVARTHI S, et al. NBTI impact on transistor and circuit: Models, mechanisms and scaling effects [MOSFETs][C]. IEEE International Electron Devices Meeting, Washington, DC, USA, 2003: 14.5.1-14.5.4.
  • 加载中
计量
  • 文章访问数:  1414
  • HTML全文浏览量:  109
  • PDF下载量:  333
  • 被引次数: 0
出版历程
  • 收稿日期:  2016-10-20
  • 修回日期:  2017-03-23
  • 刊出日期:  2017-07-19

目录

    /

    返回文章
    返回