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基于概率CMOS模型的反馈环路的数字电路容错特性分析

李妍 胡剑浩 杨泽国

李妍, 胡剑浩, 杨泽国. 基于概率CMOS模型的反馈环路的数字电路容错特性分析[J]. 电子与信息学报, 2017, 39(7): 1634-1639. doi: 10.11999/JEIT161096
引用本文: 李妍, 胡剑浩, 杨泽国. 基于概率CMOS模型的反馈环路的数字电路容错特性分析[J]. 电子与信息学报, 2017, 39(7): 1634-1639. doi: 10.11999/JEIT161096
LI Yan, HU Jianhao, YANG Zeguo. Fault-tolerant Analysis for Feedback Based Digital Circuit via Probabilistic CMOS Model[J]. Journal of Electronics & Information Technology, 2017, 39(7): 1634-1639. doi: 10.11999/JEIT161096
Citation: LI Yan, HU Jianhao, YANG Zeguo. Fault-tolerant Analysis for Feedback Based Digital Circuit via Probabilistic CMOS Model[J]. Journal of Electronics & Information Technology, 2017, 39(7): 1634-1639. doi: 10.11999/JEIT161096

基于概率CMOS模型的反馈环路的数字电路容错特性分析

doi: 10.11999/JEIT161096
基金项目: 

国家自然科学基金(61371104)

Fault-tolerant Analysis for Feedback Based Digital Circuit via Probabilistic CMOS Model

Funds: 

The National Natural Science Foundation of China (61371104)

  • 摘要: 反馈环路是模拟电路中有效容错的电路结构。反馈电路也因其存储性能而被广泛使用于数字电路的时序电路中,但是反馈电路在数字电路的组合电路的稳定特性鲜少被人研究,尤其是低功耗应用。以马氏随机场为理论的MRF电路以其低功耗下的高稳定性得到研究和关注,但其电路的反馈结构缺乏理论支持和依据,因此马氏随机场电路的容错特性未被清晰得以解释。该文以利用概率CMOS建模概率门来分析MRF核心反馈环NAND-NAND,从理论上证明了反馈电路输出的计算正确概率具有递增且上有界的特点,并数学证明了MRF的核心反馈环电路具有优于传统CMOS电路的容错性能。其理论推导结果与测试结果呈现一致性。
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出版历程
  • 收稿日期:  2016-10-17
  • 修回日期:  2017-01-24
  • 刊出日期:  2017-07-19

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