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自偏置PLL电源噪声敏感度分析

李天一 许晓冬 尹韬 韦援丰 黄国城 李威 杨海钢

李天一, 许晓冬, 尹韬, 韦援丰, 黄国城, 李威, 杨海钢. 自偏置PLL电源噪声敏感度分析[J]. 电子与信息学报, 2017, 39(7): 1646-1650. doi: 10.11999/JEIT161088
引用本文: 李天一, 许晓冬, 尹韬, 韦援丰, 黄国城, 李威, 杨海钢. 自偏置PLL电源噪声敏感度分析[J]. 电子与信息学报, 2017, 39(7): 1646-1650. doi: 10.11999/JEIT161088
LI Tianyi, XU Xiaodong, YIN Tao, WEI Yuanfeng, HUANG Guocheng, LI Wei, YANG Haigang. Sensitivity Analysis of Power Supply Noise Induced Jitter in Self Biased PLL[J]. Journal of Electronics & Information Technology, 2017, 39(7): 1646-1650. doi: 10.11999/JEIT161088
Citation: LI Tianyi, XU Xiaodong, YIN Tao, WEI Yuanfeng, HUANG Guocheng, LI Wei, YANG Haigang. Sensitivity Analysis of Power Supply Noise Induced Jitter in Self Biased PLL[J]. Journal of Electronics & Information Technology, 2017, 39(7): 1646-1650. doi: 10.11999/JEIT161088

自偏置PLL电源噪声敏感度分析

doi: 10.11999/JEIT161088
基金项目: 

国家自然科学基金(61271149, 61474120)

Sensitivity Analysis of Power Supply Noise Induced Jitter in Self Biased PLL

Funds: 

The National Natural Science Foundation of China (61271149, 61474120)

  • 摘要: 该文提出一种基于传递函数的有效方法,可以预测自偏置PLL电源噪声引起的抖动性能。PLL的复制偏置调整器的电源噪声敏感度由小信号分析提取,分析表明需要在闭环带宽和电源噪声敏感度之间做权衡。作为例子,该文分析了一款具体的自偏置PLL电路的电源噪声性能,该PLL为一款相位插值CDR提供时钟。所提方法与瞬态仿真的结果进行了对比,结果表明该方法可以预测周期抖动数值,具有相当精度。同样,该方法也对提高自偏置PLL噪声性能有指导意义。
  • MANEATIS J G. Low-jitter process-independent DLL and PLL based on self-biased techniques[J]. IEEE Journal of Solid-State Circuits, 1996, 31(11): 1723-1732. doi: 10.1109/ JSSC.1996.542317.
    MANEATIS J G, KIM J, MCCLATCHIE I, et al. Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL[J]. IEEE Journal of Solid-State Circuits, 2003, 38(11): 1795-1803. doi: 10.1109/JSSC.2003.818298.
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出版历程
  • 收稿日期:  2016-10-17
  • 修回日期:  2017-02-10
  • 刊出日期:  2017-07-19

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