超高速全并行快速傅里叶变换器

陈杰男; 费超; 袁建生; 曾维棋; 卢浩; 胡剑浩

doi:10.11999/JEIT160036

超高速全并行快速傅里叶变换器

doi: 10.11999/JEIT160036

基金项目:

国家自然科学基金(6150010678, 61371104)

计量
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- HTML全文浏览量: 175
- PDF下载量: 540
- 被引次数: 0
出版历程
- 收稿日期: 2016-01-13
- 修回日期: 2016-05-30
- 刊出日期: 2016-09-19

An Ultra-high-speed Fully-parallel Fast Fourier Transform Design

Funds:

The National Natural Science Foundation of China (6150010678, 61371104)

摘要

摘要: 设计和实现超高速快速傅里叶变换器(FFT)在雷达与未来无线通信等系统中具有重要意义。该文提出首个全并行架构的FFT处理器，其避免了复杂的路由寻址以及数据访问冲突等问题，基于较大基进行分解降低运算复杂度。由于旋转因子已知和固定，大量的乘法转化为了定系数乘法。同时由于采用了串行的计算单元，在达到全并行结构的高速度同时硬件复杂度相对较低；所有的硬件计算单元处于满载的条件，其硬件效率能达到100%。根据实际的实现结果，所提出的512点FFT处理器结构能够达到5.97倍速度面积比的提升，同时硬件开销仅占用了Xilinx V7-980t FPGA 30%的查找表资源与9%的寄存器资源。
- 快速傅里叶变换 /
- 全并行 /
- 比特串行计算 /
- 常系数乘法
Abstract: The design and implementation of ultra-high-speed FFT processor is imperative in radar system and prospective wireless communication system. In this paper, the fully-parallel-architecture FFT with bit-serial arithmetic is proposed. This method avoids the complexity of data addressing, access and routing. Based on the high-radix factorization, the multiplication number can be reduced. Out of the reason that twiddle factors are fixed in the design, constant coefficient optimization can be used in multiplications. Besides, bit-serial arithmetic cuts down the hardware cost, and makes the computation elements full-load to get a 100% efficiency. As a result, the presented 512-point FFT processer has 5.97 times gain in speed-throughput ratio while its hardware only accounts for 30% LUTs and 9% registers resource based on Xilinx V7-980t FPGA.
- Fast Fourier Transform (FFT) /
- Full parallel /
- Bit-serial calculation /
- Constant coefficient multiplication

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参考文献(16)

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