条件推测性十进制加法器的优化设计

崔晓平; 王书敏; 刘伟强; 董文雯

doi:10.11999/JEIT151416

条件推测性十进制加法器的优化设计

doi: 10.11999/JEIT151416

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出版历程
- 收稿日期: 2015-12-14
- 修回日期: 2016-06-08
- 刊出日期: 2016-10-19

Design of Optimized Conditional Speculative Decimal Adders CUI Xiaoping WANG Shumin LIU Weiqiang DONG Wenwen

摘要

摘要: 随着商业计算和金融分析等高精度计算应用领域的高速发展，提供硬件支持十进制算术运算变得越来越重要，新的IEEE 754-2008浮点运算标准也添加了十进制算术运算规范。该文采用目前最佳的条件推测性算法设计十进制加法电路，给出了基于并行前缀/进位选择结构的条件推测性十进制加法器的设计过程，并通过并行前缀单元对十进制进位选择加法器进行优化设计。采用Verilog HDL对32 bit, 64 bit和128 bit十进制加法器进行描述并在ModelSim平台上进行了仿真验证，在Nangate Open Cell 45nm标准工艺库下，通过Synopsys公司综合工具Design Compiler进行了综合。与现有的条件推测性十进制加法器相比较，综合结果显示该文所提出的十进制加法器可以提升12.3%的速度性能。
- 十进制加法 /
- 条件推测十进制加法 /
- 并行前缀 /
- 进位选择加法器
Abstract: There are increasing interests in hardware support for decimal arithmetic due to the demand of high accuracy computation in commercial computing, financial analysis, and other applications. New specifications for decimal floating-point arithmetic have been added to the revised IEEE 754-2008 standard. In this paper, the algorithm and architecture of decimal addition is studied comprehensively. A decimal adder is designed by using the parallel-prefix/carry-select architecture. The parallel-prefix unit is used to optimize the decimal carry select adder. The decimal adder has been realized by Verilog HDL and simulated with ModelSim. The synthesis results of this design by Design Compiler is also given and analyzed under Nangate Open Cell 45nm library. The results show that the delay performance of the proposed circuit can be improved by up to 12.3%.
- Decimal addition /
- Conditional speculative decimal addition /
- Parallel prefix /
- Carry select adder

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参考文献(18)

IEEE Std 754(TM)-2008. IEEE standard for floating-point arithmetic[S]. IEEE CS, 2008. doi: 10.1109/ieeestd.2008. 4610935.

EISEN L, WARD J W, TAST H W, et al. IBM POWER6 accelerators: VMX and DFU[J]. IBM Journal of Research and Development, 2007, 51(6): 663-684. doi: 10.1147/rd.516.0663.

SCHWARZ E M, KAPERNICK J S, and COWLISHAW M F. Decimal floating-point support on the IBM system z10 processor[J]. IBM Journal of Research and Development, 2009, 53(1): 4:1-4:10. doi: 10.1147/JRD.2009.5388585.

WANG L K, ERLE M A, TSEN C, et al. A survey of hardware designs for decimal arithmetic[J]. IBM Journal of Research and Development, 2010, 54(2): 8:1-8:15. doi: 10.1147/ JRD.2010.2040930.

SCHMOOKLER M and WEINBERGER A. High speed decimal addition[J]. IEEE Transactions on Computers, 1971, 20(8): 862-866. doi: 10.1109/T-C.1971.223362.

LIU Han, ZHANG Hao, and SEOK-BUM Ko. Area and power efficient decimal carry-free adder[J]. Electronics Letters, 2015, 51(23): 1852-1854. doi: 10.1049/el.2015.0786.

VAZQUEZ A and ANTELO E. Conditional speculative decimal addition[C]. Proceedings of Seventh Conference on Real Numbers and Computers, Nancy, France, 2006: 47-57.

VAZQUEZ A, ANTELO E, and MONTUSCHI P. Improved design of high-performance parallel decimal multipliers[J]. IEEE Transactions on Computers, 2010, 59(5): 679-693. doi: 10.1109/TC.2009.167.

VAZQUEZ A, ANTELO E, and BRUGUERA J. Fast radix-10 multiplication using redundant BCD codes[J]. IEEE Transactions on Computers, 2014, 63(8): 1902-1914. doi: 10.1109/TC.2014.2315626.

KORNERUP P. Reviewing high-radix signed-digit adders[J]. IEEE Transactions on Computers, 2015, 64(5): 1502-1505. doi: 10.1109/TC.2014.2329678.

MOHANTY B K. Area-delay-power efficient carry-select adder[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2014, 61(6): 418-422. doi: 10.1109/TCSII. 2014.2319695.

MATHEW S K, ANDERS M, KRISHNAMURTHY R K, et al. A 4 GHz 130 nm address generation unit with 32-bit sparse-tree adder core[J]. IEEE Journal of Solid-State Circuits, 2003, 38(5): 689-695. doi: 10.1109/JSSC.2003. 810056.

KOGGE P M and STONE H S. A parallel algorithm for efficient solution of a general class of recurrence equations[J]. IEEE Transactions on Computers, 1973, 22(8): 786-793. doi: 10.1109/TC.1973.5009159.

BRENT R P and KUNG H T. A regular layout for parallel adders[J]. IEEE Transactions on Computers, 1982, 31(3): 260-264. doi: 10.1109/TC.1982.1675982.

SKLANSKY J. Conditional-sum addition logic[J]. IRE Transactions on Electronic Computers, 1960, EC-9(2): 226-231. doi: 10.1109/TEC.1960.5219822.

HAN TACKDON and CARLSON D A. Fast area-efficient VLSI adders[C]. IEEE 8th Symposium on Computer Arithmetic, 1987: 49-56. doi: 10.1109/ARITH.1987.6158699.

DIMITRAKOPOULOS G and NIKOLOS D. High-speed parallel- prefix VLSI Ling adders[J]. IEEE Transactions on Computers, 2005, 54(2): 225-231. doi: 10.1109/TC.2005.26.

HE Yajuan and CHANG C H. A power-delay efficient hybrid carry-lookahead/carry-select based redundant binary to twos complement converter[J]. IEEE Transactions on Circuits Systems I: Regular Papers, 2008, 55(1): 336-346. doi: 10.1109/TCSI.2007.913610.

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