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基于与非锥的新型FPGA逻辑簇互连结构研究

黄志洪 杨海钢 杨立群 李威 江政泓 林郁

黄志洪, 杨海钢, 杨立群, 李威, 江政泓, 林郁. 基于与非锥的新型FPGA逻辑簇互连结构研究[J]. 电子与信息学报, 2015, 37(12): 3030-3040. doi: 10.11999/JEIT150249
引用本文: 黄志洪, 杨海钢, 杨立群, 李威, 江政泓, 林郁. 基于与非锥的新型FPGA逻辑簇互连结构研究[J]. 电子与信息学报, 2015, 37(12): 3030-3040. doi: 10.11999/JEIT150249
Huang Zhi-hong, Yang Hai-gang, Yang Li-qun, Li Wei, Jiang Zheng-hong, Lin Yu. Interconnect Architecture of a Novel And-inverter Cone Based FPGA Cluster[J]. Journal of Electronics & Information Technology, 2015, 37(12): 3030-3040. doi: 10.11999/JEIT150249
Citation: Huang Zhi-hong, Yang Hai-gang, Yang Li-qun, Li Wei, Jiang Zheng-hong, Lin Yu. Interconnect Architecture of a Novel And-inverter Cone Based FPGA Cluster[J]. Journal of Electronics & Information Technology, 2015, 37(12): 3030-3040. doi: 10.11999/JEIT150249

基于与非锥的新型FPGA逻辑簇互连结构研究

doi: 10.11999/JEIT150249
基金项目: 

国家自然科学基金(61271149)

Interconnect Architecture of a Novel And-inverter Cone Based FPGA Cluster

Funds: 

The National Natural Science Foundation of China (61271149)

  • 摘要: 该文针对新型FPGA可编程逻辑单元与非锥(And-Inverter Cone, AIC)的结构特性,提出一系列方案以得到优化的逻辑簇互连结构,包括:移除输出级交叉矩阵,单级反相交叉矩阵,低负载电路优化,将反馈和输出选择功能分开,限制AIC输出级数的基础上移除中间级交叉矩阵,与LUT架构进行混合等。通过大量的实验,得出针对面积延时积最优的AIC簇互连结构,与Altera公司的FPGA芯片Stratix-IV结构相比,该结构逻辑功能簇本身面积减小9.06%, MCNC应用电路集在基于优化的AIC FPGA架构上实现的平均面积延时积减小40.82%, VTR应用电路集平均面积延时积减小17.38%;与原有的AIC结构相比,簇面积减小23.16%, MCNC应用电路集平均面积延时减小27.15%, VTR应用电路集平均面积延时积减小15.26%。
  • Kuon I and Rose J. Measuring the gap between FPGAs and ASICs[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007, 26(2): 203-215.
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    江政泓, 林郁, 黄志洪, 等. 面向AIC结构的FPGA映射工具[J]. 电子与信息学报, 2015, 37(7): 1769-1773.
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出版历程
  • 收稿日期:  2015-02-12
  • 修回日期:  2015-09-16
  • 刊出日期:  2015-12-19

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