高级搜索

留言板

尊敬的读者、作者、审稿人, 关于本刊的投稿、审稿、编辑和出版的任何问题, 您可以本页添加留言。我们将尽快给您答复。谢谢您的支持!

姓名
邮箱
手机号码
标题
留言内容
验证码

基于与非锥的新型FPGA逻辑簇互连结构研究

黄志洪 杨海钢 杨立群 李威 江政泓 林郁

黄志洪, 杨海钢, 杨立群, 李威, 江政泓, 林郁. 基于与非锥的新型FPGA逻辑簇互连结构研究[J]. 电子与信息学报, 2015, 37(12): 3030-3040. doi: 10.11999/JEIT150249
引用本文: 黄志洪, 杨海钢, 杨立群, 李威, 江政泓, 林郁. 基于与非锥的新型FPGA逻辑簇互连结构研究[J]. 电子与信息学报, 2015, 37(12): 3030-3040. doi: 10.11999/JEIT150249
Huang Zhi-hong, Yang Hai-gang, Yang Li-qun, Li Wei, Jiang Zheng-hong, Lin Yu. Interconnect Architecture of a Novel And-inverter Cone Based FPGA Cluster[J]. Journal of Electronics & Information Technology, 2015, 37(12): 3030-3040. doi: 10.11999/JEIT150249
Citation: Huang Zhi-hong, Yang Hai-gang, Yang Li-qun, Li Wei, Jiang Zheng-hong, Lin Yu. Interconnect Architecture of a Novel And-inverter Cone Based FPGA Cluster[J]. Journal of Electronics & Information Technology, 2015, 37(12): 3030-3040. doi: 10.11999/JEIT150249

基于与非锥的新型FPGA逻辑簇互连结构研究

doi: 10.11999/JEIT150249
基金项目: 

国家自然科学基金(61271149)

Interconnect Architecture of a Novel And-inverter Cone Based FPGA Cluster

Funds: 

The National Natural Science Foundation of China (61271149)

  • 摘要: 该文针对新型FPGA可编程逻辑单元与非锥(And-Inverter Cone, AIC)的结构特性,提出一系列方案以得到优化的逻辑簇互连结构,包括:移除输出级交叉矩阵,单级反相交叉矩阵,低负载电路优化,将反馈和输出选择功能分开,限制AIC输出级数的基础上移除中间级交叉矩阵,与LUT架构进行混合等。通过大量的实验,得出针对面积延时积最优的AIC簇互连结构,与Altera公司的FPGA芯片Stratix-IV结构相比,该结构逻辑功能簇本身面积减小9.06%, MCNC应用电路集在基于优化的AIC FPGA架构上实现的平均面积延时积减小40.82%, VTR应用电路集平均面积延时积减小17.38%;与原有的AIC结构相比,簇面积减小23.16%, MCNC应用电路集平均面积延时减小27.15%, VTR应用电路集平均面积延时积减小15.26%。
  • Kuon I and Rose J. Measuring the gap between FPGAs and ASICs[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007, 26(2): 203-215.
    Mayer-Lindenberg F. Design and application of a scalable embedded systems architecture with an FPGA based operating infrastructure[C]. 9th Euromacro Conference on Digital System Design, Croatia, 2006: 189-196.
    Betz V, Rose J, and Marquardt A. Architecture and CAD for Deep-Submicron FPGAs[M]. Netherlands, Kluwer Academic Publishers, 1999: 15-20.
    Parandeh-Afshar H, Benbihi H, Novo D, et al.. Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones[C]. Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, 2012: 119-128.
    Parandeh-Afshar H, Zgheib G, Novo D, et al.. Shadow and-inverter cones[C]. IEEE International Conference on Field Programmable Logic and Applications (FPL), Porto, 2013: 1-4.
    Mishchenko A, Chatterjee S, and Brayton R. DAG-aware AIG rewriting: a fresh look at combinational logic synthesis [C]. Proceedings of the 43rd Design Automation Conference, San Francisco, 2006: 532-536.
    埃伯哈德, 蔡德勒等, 编. 李文林, 等译.《数学指南实用数学手册》[M]. 北京: 科学出版社, 2012: 875.
    Zgheib G, Yang L, Huang Z, et al.. Revisiting and-inverter cones[C]. Proceedings of the 2014 ACM/SIGDA international symposium on Field-Programmable Gate Arrays. ACM, Monterey, 2014: 45-54.
    Altera Corporation. Stratix IV Device Handbook, vols.1 and 2.[OL] https://www.altera.com/content/dam/altera-www /global/en_US/pdfs/literature/hb/strastr-iv/stratix4_handbook.pdf, 2012.
    Murray K E, Whitty S, Liu S, et al.. Titan: enabling large and complex benchmarks in academic CAD[C]. Proceedings of the 23rd International Conference on Field-Programmable Logic and Applications, Porto, Portugal, 2013: 1-8.
    Lewis D, Ahmed E, Baeckler G, et al.. The stratix II logic and routing architecture[C]. Proceedings of the 2005 ACM/ SIGDA 13th ACM International Symposium on Field- Programmable Gate Arrays, Monterey, 2005: 14-20.
    Luu J, Goeders J, Wainberg M, et al.. VTR 7.0: Next generation architecture and CAD system for FPGAs[J]. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2014, 7(2): 6:1-6:30.
    Brayton R and Mishchenko A. ABC: an academic industrial- strength verification tool[C]. Computer Aided Verification, Edinburgh, 2010: 24-40.
    江政泓, 林郁, 黄志洪, 等. 面向AIC结构的FPGA映射工具[J]. 电子与信息学报, 2015, 37(7): 1769-1773.
    Jiang Zheng-hong, Lin Yu, Huang Zhi-hong, et al.. Mapper for AIC-based FPGAs[J]. Journal of Electronics Information Technology, 2015, 37(7): 1769-1773.
    Lemieux G, Leventis P, and Lewis D. Generating highly- routable sparse crossbars for PLDs[C]. Proceedings of the 8th ACM/SIGDA International Symposium on FPGA, Monterey, California, 2000: 155-64.
  • 加载中
计量
  • 文章访问数:  1209
  • HTML全文浏览量:  97
  • PDF下载量:  539
  • 被引次数: 0
出版历程
  • 收稿日期:  2015-02-12
  • 修回日期:  2015-09-16
  • 刊出日期:  2015-12-19

目录

    /

    返回文章
    返回