Design of Multi-standard Discrete Cosine Transform Based on Coarse-grained Reconfigurable Array
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摘要: 在视频信号的编解码流程中，离散余弦变换(DCT)是一个至关重要的环节，其决定了视频压缩的质量和效率。针对88尺寸的2维离散余弦变换，该文提出一种基于粗粒度可重构阵列结构(Coarse-Grained Reconfigurable Array, CGRA)的硬件电路结构。利用粗粒度可重构阵列的可重配置的特性，实现在单一平台支持多个视频压缩编码标准的88 2维离散余弦变换。实验结果显示，这种结构每个时钟周期可以并行处理8个像素，吞吐率最高可达1.157109像素/s。与已有结构相比，设计效率和功耗效率最高可分别提升4.33倍和12.3倍，并能够以最高30帧/s的帧率解码尺寸为40962048，格式为4:2:0的视频序列。Abstract: Discrete Cosine Transform (DCT) plays an important role in the codec process of video signals, and has a significant influence on the compression efficiency and quality. In this paper, a Coarse-Grained Reconfigurable Array (CGRA) based hardware architecture is proposed for 8-point 2D DCT. Through the reconfiguration of coarse-grained reconfigurable array, the proposed architecture is capable of supporting 88 2D discrete cosine transform of the multiple video compression coding standards in a single platform. The experimental results show that the proposed architecture is able to parallel process 8 pixels in a cycle, and the throughput achieves up to 1.157109 pixels per second. The design efficiency and power efficiency is about 4.33 times and 12.3 times higher than existing works respectively. Moreover, the proposed architecture can support real-time decoding of 40962048 at 30 fps (4:2:0) video sequences.
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