Abstract: Discrete Cosine Transform (DCT) plays an important role in the codec process of video signals, and has a significant influence on the compression efficiency and quality. In this paper, a Coarse-Grained Reconfigurable Array (CGRA) based hardware architecture is proposed for 8-point 2D DCT. Through the reconfiguration of coarse-grained reconfigurable array, the proposed architecture is capable of supporting 88 2D discrete cosine transform of the multiple video compression coding standards in a single platform. The experimental results show that the proposed architecture is able to parallel process 8 pixels in a cycle, and the throughput achieves up to 1.157109 pixels per second. The design efficiency and power efficiency is about 4.33 times and 12.3 times higher than existing works respectively. Moreover, the proposed architecture can support real-time decoding of 40962048 at 30 fps (4:2:0) video sequences.