基于FPGA的数字高清晰度电视视频解码器的设计和实现
THE DESIGN AND IMPLEMENTATION OF AN FPGA-BASED DIGITAL HDTV VIDEO DECODER
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摘要: 本文介绍了一个能实时解码基于MPEG-2的高清晰度电视(HDTV)编码流的视频解码器的设计方案及其实现。在设计中采用大量FPGA以及能实现高速处理的并行处理技术和流水线工作方式,并研究了由并行处理而导致的运动补偿越界等特殊问题的解决途径。论文阐明了解码器的总体结构和各主要电路的组成以及整个解码过程的具体实现。Abstract: This paper presents the scheme and its implementation of a video decoder, which can complete real-time decoding the MPEG-2 based coded bit stream. This scheme adopts the parallel processing technique, the operation in pipe line and a large quantity of FPGA. The approach for the motion compensation crossing the border, which is caused by parallel processing, is studied. The architecture of the decoder, the formation of main circuits and the realization of decoding procedue are described.
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ISO/IEC IS 13818. Generic Coding of Moving Picture and Associated Audio. Nov. 1994.[2]周萍.数字高清晰度电视视频解码器的研究:[博士论文],天津:天津大学,1996年6月.[3]Xilinx. Inc. The Programmable Logic Data Book. 1994.[4]Grand Alliance HDTV System Specification. Version 1.0. Apr. 1994.[5]Lei S M, Sun M T. An entropy coding system for digital HDTV application. IEEE Trans. on CAS VT, 1991, 1(1): 147-155. -
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