Pangrle B M, Gajski D D. IEEE Trans. on CAD, 1987, CAD-6(6): 1098-1112.[2]Trickey H. IEEE Trans. on CAD, 1987, CAD-6(2): 259-269.[3]Sechen C, Samgiovanni-Vincentelli A. IEEE J. Solid-State Circuits, 1985, SC-20(2): 510-522.[4]VHDL Language Reference Manual: IEEE-STE-1987, IEEE Computer Society Publications Dept Piscataway, NJ, LISA: 1987.[5]Ainscough J, et al. LEE Proc.G, 1992, 139(2): 149-153.[6]Antao B A A,Brodersen A J.[J]. IEEE Design Test of Computers.1992,9(2):8-[7][7][8]Sheu B J, Lee J C, Fung A H. IEE Proc.-G, 1990, 137(4): 266-274.[9]Carley L R, et al. ACACIA: The CMU Analog Des论n System, Proc.Custom Integrated Circuits Conf., 1989, 4.3.1-4.3.5.[10]Harjani R, et al. IEEE Trans. on CAD, 1989, CAD-8(12): 1247-1265.[11]Berkcan E, et al. Analog Compilation Based on Successive Decompositions, Proc. ACM/IEEE-CS Design Automation Conf., California, USA: 1988, 369-375.[12]Klinke R, et al. Rule-Based Analog Circuit Design, European Design Automation Conf., Brussels, Belgium: 1992, 48o-484.[13]EI-Turky F 141. IEEE Trans. on CAD, 1989 CAD-8(6): 680-691.[14]Bowman R J, Lane D J. A Knowledge-Based System for Analog Integrated Circuit Design, IEEE-ICCAD Conf., Santa Clara, CA, USA: 1985.[15]Koh H Y, et al. Automatic Synthesis of Operational Apmlifiers Based on Analytical Circuits Models, IEEE-ICCAD Conf., Santa Clara, CA, USA: 1987, 502-505.[16]Stoffels J, van Reeuwijk C. AMPDES: A Progam for the Synthesis of High-Performance Amplifiers. European Design Automation Conference, Brussels, Belgium: 1992, 474-479.[17]Maulik P C. Formulations for Optimization-Based Synthesis of Analog Cells, Research Report No, CMUCAD-92-50, Oct, 1992.[18]Kon H Y, et al. IEEE Trans. on CAD, 1990, CAD-9(2): 113-125.[19]Proesmans F. Topology Selection. ESAT-MICAS Seminal, Dec. 16, 1993.[20]Onodua H. IEICE Trans., 1991, J74-A(2): 79-186.[21]Lu J Q, Adachi T. IEICE Trans, 1991, E74(5): 1011-1013.[22]Fermandz F V, et al. Symbolic Analysis of Large Analog Integrated Circuits by Approximation During Expression Generation, IEEE-ISCAS Conf., London: 1994, 1.25-1.28.[23]Gielen G G E, et al. IEEE J. of Solid-State Circuits, 1990, SC-25(3): 707-713.[24][23][25]Gielen G G E, et al. IEEE J. of Solid-State Circuits, 1989, SC-24(6): 1587-1596.[26]Shaif-Bakhtiar M, et al. IEE Proc.-G, 1993, 140(1): 68-74.[27]Brayton R K. Proc[J].IEEE.1981, 69(10):1334-1362[28]Lightner M R, Director S W. IEEE Trans. on CAS, 1981, CAS-28(2): 169-179.[29]Onoder H, et al. IEEE J. of Solid-State Circuits, 1990, SC-25(2): 446-473.[30]Nye W, et al. IEEE Trans on CAD, 1988, CAD-7(2): 501-519.[31]Shyu J-M, Sangiovanni-Vincentelli A. ECSTASY: A New Environment for IC Design Optimization IEEE-ICCAD Conf.,Santa Clara, CA, USA: 1988, 484-487.[32]Chavez J, et al. Anlog Design Optimization: A Case Study, IEEIrISCAS Conf., Chicago, Illinois, USA: 1993. 2083-2085.[33]Henderson P K. Sizing of Analog Circuits for Small-Signal Gains, European Design Automation Conf., Brussels, Belgium: 1992, 469-473.[34]Maulik P C, et al. IEEE J. of Solid-State Circuits, 1993, SG28(3): 233-241.[35]Nagaraj N S. A New Optimizer for Performance Optimization of Integrated Circuits by Device Sizing, IEEE-ISCAS Conf., San Diago, CA, USA: 1992, 2102-2105.[36]Abel C J, et al. Characterization of Transister Mismatch for Statistical CAD of Submicron CMOS Analog Circuts. IEEE-ISCAS Conf, Chicago, Illinois, USA: 1993, 1401-1404.[37]Gill P.[J].et. al. Users Guide for NPSOL 4.0. Tech. Report SOL 86-2, Stanford University.1986,:-. User' target='_blank'>[38]Rijmenants J, et al. IEEE J. of Solid-State Circuits, 1989, SG24( 2):417-425.[39][37][40]Malavasi E, et al. IEEE Trans. on CAD, 1993, CAD-12(8): 1186-1197.[41]Cohn J M, et al. IEEE J. of Solid-State Circuits, 1991 SG26(3): 330-342.Garrod D J, Device-Level Routing of Analog Cells in ANAGRAM II. Research Report No. CMUCAD-91-59, Carnegie-Mellon University, 1991.[42]Beaten V M Z, et al. IEEE J. of Solid-State Ciucuits, 1993, SC-28(3): 261-268.[43]Shiraishi Y, et al. A High-Packing Density Module ICCAD Conf., Santa Clara, CA, USA: 1990, 194-197.[44]Generation for Bipolar Analog LSIs. IEEE-[45]Mehranfor S W. IEEE J. of Solid-State Ciucuits, 1991, SG26(3):386-393.[46]Mogaki M, et al. LADIES: An Automatic Layout System for Analog LSIS. IEEE-ICCAD Conf. Santa Clara, CA, USA: 1989, 450-453.[47]Malavasi E, et al. A Routing Methodology for Analog Integrated Circuits. IEEE-ICCAD Conf. Santa Clara, CA, USA: 1990, 202-205.[48]Tani K. IEICE Trans., 1992, E75-A(10): 1286-1293.[49]Choudhury U. IEEE Trans. on CAD, 1993, CAD-12(2): 208-224.[50]Ohtsuka T. IEICE Trans., 1993, E76-A(10): 1626-1635.[51]Pillar M. Constraint Generation and Placement for Automatic Layout Design of Analog Integrated Circuits. IEEE-ISCAS Conf., London: 1994, 1.355-1.358.
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