基于时间约束的FPGA数字水印

陆健峰; 王朔中

基于时间约束的FPGA数字水印

计量
- 文章访问数: 2312
- HTML全文浏览量: 84
- PDF下载量: 698
- 被引次数: 0
出版历程
- 收稿日期: 2003-06-28
- 修回日期: 2003-10-20
- 刊出日期: 2004-12-19

FPGA Watermarking Based on Modification of Time Constraints

摘要

摘要: 该文提出一种基于时间约束的FPGA数字水印技术,其基本思想是将准备好的水印标记嵌入非关键路径上的时间约束来定制最终的下载比特流文件,同时并不改变设计的原始性能.这一方法能保证水印标记所对应的下载比特流文件的唯一性,从而可对FPGA设计模块的所有权提供强有力的证明。与其他方法相比,该文提出的技术不仅具有零空间开销和低时间开销,而且还有效地提高了信息嵌入量。
- 知识产权; 数字水印; 现场可编程门阵列; 时间约束
Abstract: Based on modification of time constraints in the FPGA design, a watermark-embedding scheme is proposed for protection of intellectual property rights of the system designer. A coded binary watermark sequence is used to replace the least significant digits of the time constraints in some non-critical paths. The modified time constraints lead to substantial and unique changes in the generated bit stream without altering the performance of the design, both in terms of space and time overheads and the system functionality. The embedded data can be extracted in a reverse procedure. The paper provides a scheme with zero area and low timing overheads, and a significant increase in embedding capacity in comparison with some existing techniques.

HTML全文

参考文献(1)

Petitcolas F A P, Anderson R J, Kuhn M G. Information hiding - A survey[J].Proc. IEEE.1999,87(7):1062-1078[2]Hartung F, Kutter M. Multimedia watermarking techniques[J].Proc. IEEE.1999, 87(7):1079-1107[3]Lach J, Mangione-Smith W H, Potkonjak M. Signature hiding techniques for FPGA intellectual property protection. International Conference on Computer-Aided Design, San Jose, CA, USA,1998: 186-189.[4]Kahng A B, et al.. Watermarking techniques for intellectual property protection. Design Automation Conference, San Francico, California, USA, 1998: 776-781.Lach J, Mangione-Smith W H, Potkonjak M. Fingerprinting digital circuits on programmable hardware. International Workshop on Information Hiding, Portland, Oregon, USA, 1998: 16-31.[5]Lach J, Mangione-Smith W H, Potkonjak M. Fingerprinting techniques for field programmable gate array intellectual property protection[J].IEEE Trans. on Computer-Aided Design.2001,20(10):1253-1261[6]Lach J, Mangione-Smith W H, Potkonjak M. Robust FPGA intellectual property protection through multiple small watermarks. Design Automation Conference, New Orleans, LA, USA,1999: 831-836.[7]Lach J, Mangione-Smith W H, Potkonjak M. Enhanced intellectual property protection for digital circuits on programmable hardware, International Workshop on Information Hiding, Dresden,Germany, 1999: 286-301.[8]Kahng A B, et al.. Constraint-based watermarking techniques for design IP protection[J].IEEE Trans. on Computer-Aided Design.2001, 20(10):1236-1252[9]Jain A K, Yuan Lin, Pari P R, Qu G. Zero overhead watermarking technique for FPGA designs.GLSVLSI, Washington, DC, USA, 2003: 147-152.[10]Lach J, Mangione-Smith W H, Potkonjak M. FPGA fingerprinting techniques for protecting intellectual property. Custom Integrated Circuits Conference, Santa Clara, CA, USA, 1998: 299-302.[11]Qu G, Potkonjak M. Fingerprinting intellectual property using constraint-addition. Proceedings of the 2000 International Symposium on Low Power Electronics and Design, Rapallo/Portofino Coast, Italy, 2000: 587-592.[12]Schouten R. A whitepaper on SRAM FPGA security. February 2003, http:∥www.fpga.com.cn/advance/skill/SRAM_Security_whitepaper.pdf.

施引文献

资源附件(0)

访问统计