一种新的集成电路互连线串扰模型和估计公式
A new kind of interconnect crosstalk model and estimation formula for high-speed integrated circuits
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摘要: 建立了一个考虑分布电阻，分布电容的互连线混П模型，在这个模型的基础上，分析了终端在最坏条件下的串扰响应，并推导了三阶S域系数的精确表达式，最终，获得了一个新的互连线串扰响应的估计公式，通过与SPICE模拟的结果相比较，该文的模拟结果非常接近实际电路的串扰响应，与相关文献所发表的结果相比较，该模型更符合实际情况，结果也更精确。Abstract: In this paper, an interconnect delay estimation model is built up, including the effect of distributed resistance, capacitance and even inductance. Then, on the basis of this model, the respondence of the terminal on the worst condition is analyzed and three-order precise formula to estimate the crosstalk respondence is presented. In the end, a new estimation formula for interconnect crosstalk respondence is derived. Moreover, experimental result is excellent enough to the simulation result of SPICE for practical circuit.
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Y. Eo, W. R. Eisenstadt, J. Y. Jeong, O. Kwon, A new on-chip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design, IEEE Trans. on Electron Devices, 2000,47(1), 129-140.[2]T. Sakurai, Closed-form expressions for interconnection delay, coupling and crosstalk in VLSIs,IEEE Trans. on Electron Devices, 1993, 40(1), 118-124.[3]J. Cong , Z. Pan, Interconnect delay estimation models for synthesis and design planning, in Proc. Asia and South Pacific Design Automation Conf., Jan. 1999, 97-100.[4]Y.I. Ismail, E. G. Friedman, J. L. Neves, Figures of merit to characterized the important of on-chip inductance, IEEE Trans. on VLSI Syst. 1999, 7(4), 442-449.[5]Semiconductor Industry Association, National Technology Roadmap for Semiconductor, USA,1997. -
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