The Research of Area-Efficiency for the Routing Channel Distribution in FPGAs

Xilinx Inc. The Programmable Logic Products Data Book 2000.[2]DeHon, Andre. Balancing interconnect and computation in a reconfigurable computing array. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, California, United States, 1999: 69-78.[3]Wilton S J E. Implementing logic in FPGA embedded memory arrays: Architectural implications. Proc IEEE Custom Integrated Circuits Conference, Santa Clara, May 1998: 1241-1244.[4]Trimberger Stephen. Effects of FPGA architecture on FPGA routing. Proceedings of the 32nd ACM/IEEE conference on Design automation, San Francisco, 1995: 574-578.[5]Masud M I, Wilton S J E. A new switch block for segmented FPGAs. International Workshop on Field Programmable Logic and Applications, Glasgow, United Kingdom, September 1999: 274-281.[6]Chow Paul, Soon O S. The design of an SRAM-based fieldprogrammable gate array-Part I: Architecture[J].IEEE Trans.onVLSI Systems.1999, 7(2):191-197[7]Khalid M, Rose J. The effect of fixed I/O positioning on theroutability and speed of FPGAs. Proc. Canadian Workshop on Field-Programmable Devices, Montreal, Canada, 1995: 94-102.[8]Yang S. Logic synthesis and optimization benchmarks, Version 3.0. Technical Report, Microelectronics Center of North Carolina, 1991.[9]Sentovich E M. SIS: A system for sequential circuit synthesis. Technical Report, No. UCB/ERL M92/41 University of California, Berkeley, May 1992.[10]Cong J, Ding Y. Flowmap: An optimal technology mapping algorithm for delay optimization in Lookup-Table based FPGA designs[J].IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems.1994, 13:1-12[11]Betz V, Rose J. VPR: A new packing, placement and routing tool for FPGA research. Seventh International Workshop on Field-Programmable Logic and Applications, London, UK, 1997: 213-222.[12]Wolf W. FPGA-Based System Design. Prentice Hall, 2004, chapter 3.1-3.3.