Liu Jian, Li Hua, Wang Chengning, Yu Sile. Design and implementation of system control for the HDTV video decoder[J]. Journal of Electronics & Information Technology, 2002, 24(4): 573-576.
Citation:
Liu Jian, Li Hua, Wang Chengning, Yu Sile. Design and implementation of system control for the HDTV video decoder[J]. Journal of Electronics & Information Technology, 2002, 24(4): 573-576.
Liu Jian, Li Hua, Wang Chengning, Yu Sile. Design and implementation of system control for the HDTV video decoder[J]. Journal of Electronics & Information Technology, 2002, 24(4): 573-576.
Citation:
Liu Jian, Li Hua, Wang Chengning, Yu Sile. Design and implementation of system control for the HDTV video decoder[J]. Journal of Electronics & Information Technology, 2002, 24(4): 573-576.
This paper presents the design and implementation of system control for HDTV video decoder. The principle of the system control is described in detail too. FPGA is adopted for its programmable and reconfigurable features. The system control works perfectly and steadily which ensures the perfect work of decoder and display buffer.
ISO/IEC 13818-1 Generic Coding of Moving Pictures and Associated Audio Information: System,Jan. 20, 1995. [2]SO/IEC 13818-2 Generic Coding of Moving Pictures and Associated Audio Information: Video,Jan. 20, 1995. [3]ATSC: ATSC Digital Television Standard, Oct. 4, 1995.[2]ATSC: Guide to the Use of the ATSC Digital Television Standard, Oct. 4, 1995.[3]K. Kawahara, H. Yamauchi, S. Okada, A single chip MPEG1 decoder, IEEE Trans. on Consumer Electronics, 1995, 41(3), 707-715.[4]Aldo Cugnini, Richard Shen, MPEG-2 video decoder for the digital HDTV grand allance system,IEEE Trans. on Consumer Electronics, 1995, 41(3), 748-752.