High Performance Implementation of Stereo Vision Matching Based on FPGA

Stereo vision system plays important role in three-dimensional information perception. Due to the high computational complexity, real-time processing of stereo vision needs to use dedicated hardware. However, performance requirements conflict with hardware resources in existing implementations. With the resolution increased, system requires larger disparity range and higher processing speed. In this paper, a stereo vision implementation is proposed using fine-grain pipelined structure and sub-module parallelism to improve performance. The implemented matching algorithm used adaptive correlation window strategy to raise disparity quality at object borders and integrated left-right consistency check to reduce possible errors in general. The entire stereo matching process is realized using a single chip of Field Programmable Gate Array (FPGA) and extended disparity search range to 128 pixels under limited resources. The matching process is capable of generating disparities at more than 60 frames per second on 512512 images when clocked at 60 MHz.