An Efficient Parallel Architecture for One-bit Transform Based Motion Estimation

Chen  Yun-Bi; Guo  Li; Li Zheng-Dong; Chi Ling-Hong

doi:10.3724/SP.J.1146.2010.00636

Volume 33 Issue 3

Mar. 2011

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Article Navigation > Journal of Electronics & Information Technology > 2011 > 33(3): 717-722

Chen Yun-Bi, Guo Li, Li Zheng-Dong, Chi Ling-Hong. An Efficient Parallel Architecture for One-bit Transform Based Motion Estimation[J]. Journal of Electronics & Information Technology, 2011, 33(3): 717-722. doi: 10.3724/SP.J.1146.2010.00636

Citation:

Chen Yun-Bi, Guo Li, Li Zheng-Dong, Chi Ling-Hong. An Efficient Parallel Architecture for One-bit Transform Based Motion Estimation[J]. Journal of Electronics & Information Technology, 2011, 33(3): 717-722. doi: 10.3724/SP.J.1146.2010.00636

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An Efficient Parallel Architecture for One-bit Transform Based Motion Estimation

doi: 10.3724/SP.J.1146.2010.00636

Received Date: 2010-06-28
Rev Recd Date: 2010-09-10
Publish Date: 2011-03-19

Abstract

Abstract

In order to meet the processing requirements of portable real-time full HD video compression, this paper proposes a novel macroblock-level parallel architecture based on 1-D source pixels based linear array, which overcomes the problem of massive amount of resources and large delay caused by 2-D arrays used in literatures. The proposed architecture is easy to extend and area-economical. Furthermore, towards the system bottlenecks, systolic cell and data memory organization, optimized structure are presented. Compared with the traditional architecture, the proposed architecture can achieve the improvements of speed and area at the same time. FPGA implementation results show that, LUTs is reduced by 43%, DFFs is reduced by 25%, BRAMs is reduced by 75%, and performance is increased by 32%.
- Motion estimation,
- One-bit transform,
- Hardware architecture,
- Parallel processing,
- Systolic arrays

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References

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